Graphics processor power management contexts and sequential control loops

ABSTRACT

One or more system, apparatus, method, and computer readable media is described below for power management of one or more graphics processor resources. In some embodiments, a graphics processor context associated with an application an including power-related hardware configuration and control parameters is stored to memory. In some embodiments, graphics processor contexts are switched in and out as different application workloads are processed by resources of the graphics processor. In some embodiments, power-performance management algorithms are grouped and sequentially executed in ordered phases of a control loop to generate a compatible set of control parameter requests. Once finalized, the set is output as requests to graphics processor hardware and/or updates to stored graphics processor contexts.

BACKGROUND

Many computing platforms or systems employ a graphics processor as asubsystem that performs image processing/rendering and/or parallelcomputation. A graphics processor may consume large amounts of power.Mobile computing platforms operating under stringent power constraints(e.g., to maximize battery charge duration) typically attempt to managegraphics power and performance controls, for example by placing variouscomponents of the computing system in different performance states.Conventional power management algorithms may however perform poorly inuse cases where multiple applications are sending workloads to agraphics processor concurrently, for example in platforms operating inpartial-screen and/or multi-display modes.

Also, many graphics power management systems today entail a number ofalgorithms and systems that independently attempt to improve specificaspects of power efficiency, operating as a patchwork rather than acohesive unit. With no clear ownership of power-performance controls,current solutions rely on inter-algorithm communication to preventgraphics processor resource access conflicts. As such, it is left to thedeveloper of each algorithm to track dependencies with supplementalalgorithms, a problem that increases in complexity with each new powermanagement algorithm introduced. Competition between algorithms furthercomplicates integrating new techniques into a power managementarchitecture as competition between algorithms becomes more likely.

A graphics processing subsystem that is able to achieve greater powerefficiency and/or unify the graphics power management architecture wouldtherefore be advantageous in the marketplace.

BRIEF DESCRIPTION OF THE DRAWINGS

The material described herein is illustrated by way of example and notby way of limitation in the accompanying figures. For simplicity andclarity of illustration, elements illustrated in the figures are notnecessarily drawn to scale. For example, the dimensions of some elementsmay be exaggerated relative to other elements for clarity. Further,where considered appropriate, reference labels have been repeated amongthe figures to indicate corresponding or analogous elements. In thefigures:

FIG. 1 is a block diagram of a data processing system, according to someembodiments.

FIG. 2 is a block diagram of an embodiment of a processor having one ormore processors cores, an integrated memory controller, and anintegrated graphics processor, according to some embodiments.

FIG. 3 is a block diagram of a graphics processor, according to someembodiments;

FIG. 4 is a block diagram of an embodiment of a graphics processingengine for a graphics processor, according to some embodiments;

FIG. 5 is a block diagram of another embodiment of a graphics processor,according to some embodiments;

FIG. 6 illustrates thread execution logic including an array ofprocessing elements employed in a graphics processing engine, accordingto some embodiments;

FIG. 7 is a block diagram illustrating a graphics processor executionunit instruction format, according to some embodiments;

FIG. 8 is a block diagram of another embodiment of a graphics processor,which includes a graphics pipeline, a media pipeline, a display engine,thread execution logic, and a render output pipeline, according to someembodiments;

FIG. 9A is a block diagram illustrating a graphics processor commandformat, according to some embodiments;

FIG. 9B is a block diagram illustrating a graphics processor commandsequence, according to some embodiments;

FIG. 10 illustrates exemplary graphics software architecture for a dataprocessing system, according to some embodiments;

FIG. 11 is a block diagram illustrating a graphics processor powermanagement architecture, in accordance with some embodiments;

FIG. 12 is a flow chart illustrating a graphics processor powermanagement method employing a graphics processor context, in accordancewith some embodiments;

FIG. 13A illustrates a graphics processor context data structure, storedin a memory in accordance with some embodiments;

FIG. 13B illustrates a graphics processor context as a graphicsprocessor power management method is performed, in accordance with someembodiments;

FIG. 14 is a flow diagram illustrating a power-performance method basedon either global or context-specific graphics processor performancetargets, in accordance with some embodiments;

FIG. 15 is a block diagram illustrating global and context-level powermanagement and workload scheduling on graphics processor resources, inaccordance with some embodiments;

FIG. 16 is a flow diagram illustrating a phased graphics processor powermanagement method employing a sequential control loop, in accordancewith some embodiments;

FIG. 17 is a block diagram further illustrating a phased graphicsprocessor power management architecture employing a sequential controlloop, in accordance with some embodiments; and

FIG. 18 is a parallel flow chart depicting interactions of components ina system managing power-performance of graphics workload processingassociated with multiple applications, in accordance with someembodiments.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

One or more embodiments are described with reference to the enclosedfigures. While specific configurations and arrangements are depicted anddiscussed in detail, it should be understood that this is done forillustrative purposes only. Persons skilled in the relevant art willrecognize that other configurations and arrangements are possiblewithout departing from the spirit and scope of the description. It willbe apparent to those skilled in the relevant art that techniques and/orarrangements described herein may be employed in a variety of othersystems and applications beyond what is described in detail herein.

Reference is made in the following detailed description to theaccompanying drawings, which form a part hereof and illustrate exemplaryembodiments. Further, it is to be understood that other embodiments maybe utilized and structural and/or logical changes may be made withoutdeparting from the scope of claimed subject matter. Therefore, thefollowing detailed description is not to be taken in a limiting senseand the scope of claimed subject matter is defined solely by theappended claims and their equivalents.

In the following description, numerous details are set forth, however,it will be apparent to one skilled in the art, that embodiments may bepracticed without these specific details. Well-known methods and devicesare shown in block diagram form, rather than in detail, to avoidobscuring more significant aspects. References throughout thisspecification to “an embodiment” or “one embodiment” mean that aparticular feature, structure, function, or characteristic described inconnection with the embodiment is included in at least one embodiment.Thus, the appearances of the phrase “in an embodiment,” “in oneembodiment,” or “in some embodiments” in various places throughout thisspecification are not necessarily referring to the same embodiment(s).Furthermore, the particular features, structures, functions, orcharacteristics described in the context of an embodiment, or “someembodiments” may be combined in any suitable manner in one or moreembodiments. For example, a first embodiment may be combined with asecond embodiment anywhere the particular features, structures,functions, or characteristics associated with the two embodiments arenot mutually exclusive.

As used in the description of the exemplary embodiments and in theappended claims, the singular forms “a”, “an” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will also be understood that the term “and/or” as usedherein refers to and encompasses any and all possible combinations ofone or more of the associated listed items.

Unless otherwise specified, the terms “substantially,” “close,”“approximately,” “near,” and “about” employed herein refer a margin of+/−20% of a nominal or target value. Unless otherwise specified the useof the ordinal adjectives “first,” “second,” and “third,” etc., todescribe a common object, merely indicate that different instances oflike objects are being referred to, and are not intended to imply thatthe objects so described must be in a given sequence, either temporally,spatially, in ranking or in any other manner.

As used throughout the description, and in the claims, a list of itemsjoined by the term “at least one of” or “one or more of” can mean anycombination of the listed terms. For example, the phrase “at least oneof A, B or C” can mean A; B; C; A and B; A and C; B and C; or A, B andC.

The terms “coupled” and “connected,” along with their derivatives, maybe used herein to describe functional or structural relationshipsbetween components. It should be understood that these terms are notintended as synonyms for each other. Rather, in particular embodiments,“connected” may be used to indicate that two or more elements are indirect physical, optical, or electrical contact with each other.“Coupled” may be used to indicated that two or more elements are ineither direct or indirect (with other intervening elements between them)physical, optical, or electrical contact with each other, and/or thatthe two or more elements co-operate or interact with each other (e.g.,as in a cause an effect relationship).

Some portions of the detailed descriptions provide herein are presentedin terms of algorithms and symbolic representations of operations ondata bits within a computer memory. Unless specifically statedotherwise, as apparent from the following discussion, it is appreciatedthat throughout the description, discussions utilizing terms such as“calculating,” “computing,” “determining” “estimating” “storing”“collecting” “displaying,” “receiving,” “consolidating,” “generating,”“updating,” or the like, refer to the action and processes of a computersystem, or similar electronic computing device, that manipulates andtransforms data represented as physical (electronic) quantities withinthe computer system's circuitry including registers and memories intoother data similarly represented as physical quantities within thecomputer system memories or registers or other such information storage,transmission or display devices.

One or more system, apparatus, method, and computer readable media isdescribed below for automated power-performance management of graphicsprocessor (GP) resources. In some embodiments, graphics processorconfiguration information and power management state information isstored in memory in association with an application. Such graphicsprocessor contexts are then utilized to ensure appropriate graphicsprocessor resources are timely switched-in and/or switched/out asspecific workloads are processed. In this manner, power managementcontrol is extended to the granularity of specific application render orcompute work. In some embodiments, historical state information ismaintained in association with particular contexts across execution ofmultiple workloads. Graphics processor contexts may be updated as neededbased on one or more power-performance management algorithm evaluatedduring execution of workloads. In some embodiments, graphicspower-performance management evaluation interval is partitioned intophases with algorithms executed in each phase to determine one or morepower-performance parameter in a set of values that are collected andoutput during a final phase. In some further embodiments, phasedgraphics power-performance management is integrated with graphicsprocessor contexts to implement fast (e.g., nanosecond) and slow (e.g.,millisecond) power-performance control loops.

System Overview

FIG. 1 is a block diagram of a data processing system 100, according toan embodiment. Data processing system 100 includes one or moreprocessors 102 and one or more graphics processors 108, and may be asingle processor desktop system, a multiprocessor workstation system, ora server system having a large number of processors 102 or processorcores 107. In on embodiment, the data processing system 100 is asystem-on-a-chip (SoC) integrated circuit for use in mobile, handheld,or embedded devices.

An embodiment of data processing system 100 can include, or beincorporated within a server-based gaming platform, a game console,including a game and media console, a mobile gaming console, a handheldgame console, or an online game console. In some embodiments, dataprocessing system 100 is a mobile phone, smart phone, tablet computingdevice or mobile Internet device. Data processing system 100 can alsoinclude, couple with, or be integrated within a wearable device, such asa smart watch wearable device, smart eyewear device, augmented realitydevice, or virtual reality device. In some embodiments, data processingsystem 100 is a television or set top box device having one or moreprocessors 102 and a graphical interface generated by one or moregraphics processors 108.

In some embodiments, the one or more processors 102 each include one ormore processors cores 107 to process instructions which, when executed,perform operations for system and user software. In some embodiments,each of the one or more processors cores 107 is configured to process aspecific instruction set 109. In some embodiments, instruction set 109may facilitate Complex Instruction Set Computing (CISC), ReducedInstruction Set Computing (RISC), or computing via a Very LongInstruction Word (VLIW). Multiple processor cores 107 may each process adifferent instruction set 109, which may include instructions tofacilitate the emulation of other instruction sets. Processor core 107may also include other processing devices, such a Digital SignalProcessor (DSP).

In some embodiments, the processor 102 includes cache memory 104.Depending on the architecture, the processor 102 can have a singleinternal cache or multiple levels of internal cache. In someembodiments, the cache memory is shared among various components of theprocessor 102. In some embodiments, the processor 102 also uses anexternal cache (e.g., a Level-3 (L3) cache or Last Level Cache (LLC))(not shown), which may be shared among processor cores 107 using knowncache coherency techniques. A register file 106 is additionally includedin processor 102 which may include different types of registers forstoring different types of data (e.g., integer registers, floating pointregisters, status registers, and an instruction pointer register). Someregisters may be general-purpose registers, while other registers may bespecific to the design of the processor 102.

In some embodiments, processor 102 is coupled to a processor bus 110 totransmit data signals between processor 102 and other components insystem 100. System 100 uses an exemplary ‘hub’ system architecture,including a memory controller hub 116 and an input output (I/O)controller hub 130. Memory controller hub 116 facilitates communicationbetween a memory device and other components of system 100, while I/OController Hub (ICH) 130 provides connections to I/O devices via a localI/O bus.

Memory device 120 can be a dynamic random access memory (DRAM) device, astatic random access memory (SRAM) device, flash memory device, or someother memory device having suitable performance to serve as processmemory. Memory 120 can store data 122 and instructions 121 for use whenprocessor 102 executes a process. Memory controller hub 116 also coupleswith an optional external graphics processor 112, which may communicatewith the one or more graphics processors 108 in processors 102 toperform graphics and media operations.

In some embodiments, ICH 130 enables peripherals to connect to memory120 and processor 102 via a high-speed I/O bus. The I/O peripheralsinclude an audio controller 146, a firmware interface 128, a wirelesstransceiver 126 (e.g., Wi-Fi, Bluetooth), a data storage device 124(e.g., hard disk drive, flash memory, etc.), and a legacy I/O controllerfor coupling legacy (e.g., Personal System 2 (PS/2)) devices to thesystem. One or more Universal Serial Bus (USB) controllers 142 connectinput devices, such as keyboard and mouse 144 combinations. A networkcontroller 134 may also couple to ICH 130. In some embodiments, ahigh-performance network controller (not shown) couples to processor bus110.

FIG. 2 is a block diagram of an embodiment of a processor 200 having oneor more processors cores 202A-N, an integrated memory controller 214,and an integrated graphics processor 208. Those elements of FIG. 2having the same reference numbers (or names) as the elements of anyother figure herein can operate or function in any manner similar tothat described elsewhere herein, but are not limited to such. Processor200 can include additional cores up to and including additional core202N represented by the dashed lined boxes. Each of cores 202A-Nincludes one or more internal cache units 204A-N. In some embodimentseach core also has access to one or more shared cached units 206.

The internal cache units 204A-N and shared cache units 206 represent acache memory hierarchy within the processor 200. The cache memoryhierarchy may include at least one level of instruction and data cachewithin each core and one or more levels of shared mid-level cache, suchas a Level 2 (L2), Level 3 (L3), Level 4 (L4), or other levels of cache,where the highest level of cache before external memory is classified asthe LLC. In some embodiments, cache coherency logic maintains coherencybetween the various cache units 206 and 204A-N.

In some embodiments, processor 200 may also include a set of one or morebus controller units 216 and a system agent 210. The one or more buscontroller units manage a set of peripheral buses, such as one or morePeripheral Component Interconnect buses (e.g., PCI, PCI Express). Systemagent 210 provides management functionality for the various processorcomponents. In some embodiments, system agent 210 includes one or moreintegrated memory controllers 214 to manage access to various externalmemory devices (not shown).

In some embodiments, one or more of the cores 202A-N include support forsimultaneous multi-threading. In such embodiment, the system agent 210includes components for coordinating and operating cores 202A-N duringmulti-threaded processing. System agent 210 may additionally include apower control unit (PCU), which includes logic and components toregulate the power state of cores 202A-N and graphics processor 208.

In some embodiments, processor 200 additionally includes graphicsprocessor 208 to execute graphics processing operations. In someembodiments, the graphics processor 208 couples with the set of sharedcache units 206, and the system agent unit 210, including the one ormore integrated memory controllers 214. In some embodiments, a displaycontroller 211 is coupled with the graphics processor 208 to drivegraphics processor output to one or more coupled displays. In someembodiments, display controller 211 may be separate module coupled withthe graphics processor via at least one interconnect, or may beintegrated within the graphics processor 208 or system agent 210.

In some embodiments, a ring based interconnect unit 212 is used tocouple the internal components of the processor 200. However, analternative interconnect unit may be used, such as a point-to-pointinterconnect, a switched interconnect, or other techniques, includingtechniques well known in the art. In some embodiments, graphicsprocessor 208 couples with the ring interconnect 212 via an I/O link213.

The exemplary I/O link 213 represents at least one of multiple varietiesof I/O interconnects, including an on package I/O interconnect whichfacilitates communication between various processor components and ahigh-performance embedded memory module 218, such as an eDRAM module. Insome embodiments, each of the cores 202-N and graphics processor 208 useembedded memory modules 218 as a shared Last Level Cache.

In some embodiments, cores 202A-N are homogenous cores executing thesame instruction set architecture. In another embodiment, cores 202A-Nare heterogeneous in terms of instruction set architecture (ISA), whereone or more of cores 202A-N execute a first instruction set, while atleast one of the other cores executes a subset of the first instructionset or a different instruction set.

In some embodiments, processor 200 is a part of, or implemented on, oneor more substrates using any of a number of process technologies, forexample, Complementary metal-oxide-semiconductor (CMOS), BipolarJunction/Complementary metal-oxide-semiconductor (BiCMOS) or N-typemetal-oxide-semiconductor logic (NMOS). Additionally, processor 200 canbe implemented on one or more chips or as a System-On-Chip (SOC)integrated circuit having the illustrated components, in addition toother components.

FIG. 3 is a block diagram of a graphics processor 300, which may be adiscrete graphics processing unit, or may be a graphics processorintegrated with a plurality of processing cores. In some embodiments,the graphics processor communicates via a memory mapped I/O interface toregisters on the graphics processor and with commands placed into theprocessor memory. In some embodiments, graphics processor 300 includes amemory interface 314 to access memory. Memory interface 314 can be aninterface to local memory, one or more internal caches, one or moreshared external caches, and/or to system memory.

In some embodiments, graphics processor 300 also includes a displaycontroller 302 to drive display output data to a display device 320.Display controller 302 includes hardware for one or more overlay planesfor the display and composition of multiple layers of video or userinterface elements. In some embodiments, graphics processor 300 includesa video codec engine 306 to encode, decode, or transcode media to, from,or between one or more media encoding formats, including, but notlimited to Moving Picture Experts Group (MPEG) formats such as MPEG-2,Advanced Video Coding (AVC) formats such as H.264/MPEG-4 AVC, as well asthe Society of Motion Picture & Television Engineers (SMPTE) 421M/VC-1,and Joint Photographic Experts Group (JPEG) formats such as JPEG, andMotion JPEG (MJPEG) formats.

In some embodiments, graphics processor 300 includes a block imagetransfer (BLIT) engine 304 to perform two-dimensional (2D) rasterizeroperations including, for example, bit-boundary block transfers.However, in one embodiment, 2D graphics operations are performed usingone or more components of the graphics-processing engine (GPE) 310. Insome embodiments, graphics-processing engine 310 is a compute engine forperforming graphics operations, including three-dimensional (3D)graphics operations and media operations.

In some embodiments, GPE 310 includes a 3D pipeline 312 for performing3D operations, such as rendering three-dimensional images and scenesusing processing functions that act upon 3D primitive shapes (e.g.,rectangle, triangle, etc.). The 3D pipeline 312 includes programmableand fixed function elements that perform various tasks within theelement and/or spawn execution threads to a 3D/Media sub-system 315.While 3D pipeline 312 can be used to perform media operations, anembodiment of GPE 310 also includes a media pipeline 316 that isspecifically used to perform media operations, such as videopost-processing and image enhancement.

In some embodiments, media pipeline 316 includes fixed function orprogrammable logic units to perform one or more specialized mediaoperations, such as video decode acceleration, video de-interlacing, andvideo encode acceleration in place of, or on behalf of video codecengine 306. In some embodiments, media pipeline 316 additionallyincludes a thread spawning unit to spawn threads for execution on3D/Media sub-system 315. The spawned threads perform computations forthe media operations on one or more graphics execution units included in3D/Media sub-system 315.

In some embodiments, 3D/Media subsystem 315 includes logic for executingthreads spawned by 3D pipeline 312 and media pipeline 316. In oneembodiment, the pipelines send thread execution requests to 3D/Mediasubsystem 315, which includes thread dispatch logic for arbitrating anddispatching the various requests to available thread executionresources. The execution resources include an array of graphicsexecution units to process the 3D and media threads. In someembodiments, 3D/Media subsystem 315 includes one or more internal cachesfor thread instructions and data. In some embodiments, the subsystemalso includes shared memory, including registers and addressable memory,to share data between threads and to store output data.

3D/Media Processing

FIG. 4 is a block diagram of a graphics processing engine 410 of agraphics processor in accordance with some embodiments. In oneembodiment, the GPE 410 is a version of the GPE 310 shown in FIG. 3.Elements of FIG. 4 having the same reference numbers (or names) as theelements of any other figure herein can operate or function in anymanner similar to that described elsewhere herein, but are not limitedto such.

In some embodiments, GPE 410 couples with a command streamer 403, whichprovides a command stream to the GPE 3D and media pipelines 412, 416. Insome embodiments, command streamer 403 is coupled to memory, which canbe system memory, or one or more of internal cache memory and sharedcache memory. In some embodiments, command streamer 403 receivescommands from the memory and sends the commands to 3D pipeline 412and/or media pipeline 416. The 3D and media pipelines process thecommands by performing operations via logic within the respectivepipelines or by dispatching one or more execution threads to anexecution unit array 414. In some embodiments, execution unit array 414is scalable, such that the array includes a variable number of executionunits based on the target power and performance level of GPE 410.

In some embodiments, a sampling engine 430 couples with memory (e.g.,cache memory or system memory) and execution unit array 414. In someembodiments, sampling engine 430 provides a memory access mechanism forexecution unit array 414 that allows execution array 414 to readgraphics and media data from memory. In some embodiments, samplingengine 430 includes logic to perform specialized image samplingoperations for media.

In some embodiments, the specialized media sampling logic in samplingengine 430 includes a de-noise/de-interlace module 432, a motionestimation module 434, and an image scaling and filtering module 436. Insome embodiments, de-noise/de-interlace module 432 includes logic toperform one or more of a de-noise or a de-interlace algorithm on decodedvideo data. The de-interlace logic combines alternating fields ofinterlaced video content into a single fame of video. The de-noise logicreduces or removes data noise from video and image data. In someembodiments, the de-noise logic and de-interlace logic are motionadaptive and use spatial or temporal filtering based on the amount ofmotion detected in the video data. In some embodiments, thede-noise/de-interlace module 432 includes dedicated motion detectionlogic (e.g., within the motion estimation engine 434).

In some embodiments, motion estimation engine 434 provides hardwareacceleration for video operations by performing video accelerationfunctions such as motion vector estimation and prediction on video data.The motion estimation engine determines motion vectors that describe thetransformation of image data between successive video frames. In someembodiments, a graphics processor media codec uses video motionestimation engine 434 to perform operations on video at the macro-blocklevel that may otherwise be too computationally intensive to performwith a general-purpose processor. In some embodiments, motion estimationengine 434 is generally available to graphics processor components toassist with video decode and processing functions that are sensitive oradaptive to the direction or magnitude of the motion within video data.

In some embodiments, image scaling and filtering module 436 performsimage-processing operations to enhance the visual quality of generatedimages and video. In some embodiments, scaling and filtering module 436processes image and video data during the sampling operation beforeproviding the data to execution unit array 414.

In some embodiments, the GPE 410 includes a data port 444, whichprovides an additional mechanism for graphics subsystems to accessmemory. In some embodiments, data port 444 facilitates memory access foroperations including render target writes, constant buffer reads,scratch memory space reads/writes, and media surface accesses. In someembodiments, data port 444 includes cache memory space to cache accessesto memory. The cache memory can be a single data cache or separated intomultiple caches for the multiple subsystems that access memory via thedata port (e.g., a render buffer cache, a constant buffer cache, etc.).In some embodiments, threads executing on an execution unit in executionunit array 414 communicate with the data port by exchanging messages viaa data distribution interconnect that couples each of the sub-systems ofGPE 410.

Execution Units

FIG. 5 is a block diagram of another embodiment of a graphics processor500. Elements of FIG. 5 having the same reference numbers (or names) asthe elements of any other figure herein can operate or function in anymanner similar to that described elsewhere herein, but are not limitedto such.

In some embodiments, graphics processor 500 includes a ring interconnect502, a pipeline front-end 504, a media engine 537, and graphics cores580A-N. In some embodiments, ring interconnect 502 couples the graphicsprocessor to other processing units, including other graphics processorsor one or more general-purpose processor cores. In some embodiments, thegraphics processor is one of many processors integrated within amulti-core processing system.

In some embodiments, graphics processor 500 receives batches of commandsvia ring interconnect 502. The incoming commands are interpreted by acommand streamer 503 in the pipeline front-end 504. In some embodiments,graphics processor 500 includes scalable execution logic to perform 3Dgeometry processing and media processing via the graphics core(s)580A-N. For 3D geometry processing commands, command streamer 503supplies commands to geometry pipeline 536. For at least some mediaprocessing commands, command streamer 503 supplies the commands to avideo front end 534, which couples with a media engine 537. In someembodiments, media engine 537 includes a Video Quality Engine (VQE) 530for video and image post-processing and a multi-format encode/decode(MFX) 533 engine to provide hardware-accelerated media data encode anddecode. In some embodiments, geometry pipeline 536 and media engine 537each generate execution threads for the thread execution resourcesprovided by at least one graphics core 580A.

In some embodiments, graphics processor 500 includes scalable threadexecution resources featuring modular cores 580A-N (sometimes referredto as core slices), each having multiple sub-cores 550A-N, 560A-N(sometimes referred to as core sub-slices). In some embodiments,graphics processor 500 can have any number of graphics cores 580Athrough 580N. In some embodiments, graphics processor 500 includes agraphics core 580A having at least a first sub-core 550A and a secondcore sub-core 560A. In other embodiments, the graphics processor is alow power processor with a single sub-core (e.g., 550A). In someembodiments, graphics processor 500 includes multiple graphics cores580A-N, each including a set of first sub-cores 550A-N and a set ofsecond sub-cores 560A-N. Each sub-core in the set of first sub-cores550A-N includes at least a first set of execution units 552A-N andmedia/texture samplers 554A-N. Each sub-core in the set of secondsub-cores 560A-N includes at least a second set of execution units562A-N and samplers 564A-N. In some embodiments, each sub-core 550A-N,560A-N shares a set of shared resources 570A-N. In some embodiments, theshared resources include shared cache memory and pixel operation logic.Other shared resources may also be included in the various embodimentsof the graphics processor.

FIG. 6 illustrates thread execution logic 600 including an array ofprocessing elements employed in some embodiments of a GPE. Elements ofFIG. 6 having the same reference numbers (or names) as the elements ofany other figure herein can operate or function in any manner similar tothat described elsewhere herein, but are not limited to such.

In some embodiments, thread execution logic 600 includes a pixel shader602, a thread dispatcher 604, instruction cache 606, a scalableexecution unit array including a plurality of execution units 608A-N, asampler 610, a data cache 612, and a data port 614. In one embodimentthe included components are interconnected via an interconnect fabricthat links to each of the components. In some embodiments, threadexecution logic 600 includes one or more connections to memory, such assystem memory or cache memory, through one or more of instruction cache606, data port 614, sampler 610, and execution unit array 608A-N. Insome embodiments, each execution unit (e.g. 608A) is an individualvector processor capable of executing multiple simultaneous threads andprocessing multiple data elements in parallel for each thread. In someembodiments, execution unit array 608A-N includes any number individualexecution units.

In some embodiments, execution unit array 608A-N is primarily used toexecute “shader” programs. In some embodiments, the execution units inarray 608A-N execute an instruction set that includes native support formany standard 3D graphics shader instructions, such that shader programsfrom graphics libraries (e.g., Direct 3D and OpenGL) are executed with aminimal translation. The execution units support vertex and geometryprocessing (e.g., vertex programs, geometry programs, vertex shaders),pixel processing (e.g., pixel shaders, fragment shaders) andgeneral-purpose processing (e.g., compute and media shaders).

Each execution unit in execution unit array 608A-N operates on arrays ofdata elements. The number of data elements is the “execution size,” orthe number of channels for the instruction. An execution channel is alogical unit of execution for data element access, masking, and flowcontrol within instructions. The number of channels may be independentof the number of physical Arithmetic Logic Units (ALUs) or FloatingPoint Units (FPUs) for a particular graphics processor. In someembodiments, execution units 608A-N support integer and floating-pointdata types.

The execution unit instruction set includes single instruction multipledata (SIMD) instructions. The various data elements can be stored as apacked data type in a register and the execution unit will process thevarious elements based on the data size of the elements. For example,when operating on a 256-bit wide vector, the 256 bits of the vector arestored in a register and the execution unit operates on the vector asfour separate 64-bit packed data elements (Quad-Word (QW) size dataelements), eight separate 32-bit packed data elements (Double Word (DW)size data elements), sixteen separate 16-bit packed data elements (Word(W) size data elements), or thirty-two separate 8-bit data elements(byte (B) size data elements). However, different vector widths andregister sizes are possible.

One or more internal instruction caches (e.g., 606) are included in thethread execution logic 600 to cache thread instructions for theexecution units. In some embodiments, one or more data caches (e.g.,612) are included to cache thread data during thread execution. In someembodiments, sampler 610 is included to provide texture sampling for 3Doperations and media sampling for media operations. In some embodiments,sampler 610 includes specialized texture or media sampling functionalityto process texture or media data during the sampling process beforeproviding the sampled data to an execution unit.

During execution, the graphics and media pipelines send threadinitiation requests to thread execution logic 600 via thread spawningand dispatch logic. In some embodiments, thread execution logic 600includes a local thread dispatcher 604 that arbitrates thread initiationrequests from the graphics and media pipelines and instantiates therequested threads on one or more execution units 608A-N. For example,the geometry pipeline (e.g., 536 of FIG. 5) dispatches vertexprocessing, tessellation, or geometry processing threads to threadexecution logic 600 (FIG. 6). In some embodiments, thread dispatcher 604can also process runtime thread spawning requests from the executingshader programs.

Once a group of geometric objects have been processed and rasterizedinto pixel data, pixel shader 602 is invoked to further compute outputinformation and cause results to be written to output surfaces (e.g.,color buffers, depth buffers, stencil buffers, etc.). In someembodiments, pixel shader 602 calculates the values of the variousvertex attributes that are to be interpolated across the rasterizedobject. In some embodiments, pixel shader 602 then executes anAPI-supplied pixel shader program. To execute the pixel shader program,pixel shader 602 dispatches threads to an execution unit (e.g., 608A)via thread dispatcher 604. In some embodiments, pixel shader 602 usestexture sampling logic in sampler 610 to access texture data in texturemaps stored in memory. Arithmetic operations on the texture data and theinput geometry data compute pixel color data for each geometricfragment, or discards one or more pixels from further processing.

In some embodiments, the data port 614 provides a memory accessmechanism for the thread execution logic 600 output processed data tomemory for processing on a graphics processor output pipeline. In someembodiments, the data port 614 includes or couples to one or more cachememories (e.g., data cache 612) to cache data for memory access via thedata port.

FIG. 7 is a block diagram illustrating a graphics processor executionunit instruction format 700 according to some embodiments. In one ormore embodiment, the graphics processor execution units support aninstruction set having instructions in multiple formats. The solid linedboxes illustrate the components that are generally included in anexecution unit instruction, while the dashed lines include componentsthat are optional or that are only included in a sub-set of theinstructions. In some embodiments, instruction format 700 described andillustrated are macro-instructions, in that they are instructionssupplied to the execution unit, as opposed to micro-operations resultingfrom instruction decode once the instruction is processed.

In some embodiments, the graphics processor execution units nativelysupport instructions in a 128-bit format 710. A 64-bit compactedinstruction format 730 is available for some instructions based on theselected instruction, instruction options, and number of operands. Thenative 128-bit format 710 provides access to all instruction options,while some options and operations are restricted in the 64-bit format730. The native instructions available in the 64-bit format 730 vary byembodiment. In some embodiments, the instruction is compacted in partusing a set of index values in an index field 713. The execution unithardware references a set of compaction tables based on the index valuesand uses the compaction table outputs to reconstruct a nativeinstruction in the 128-bit format 710.

For each format, instruction opcode 712 defines the operation that theexecution unit is to perform. The execution units execute eachinstruction in parallel across the multiple data elements of eachoperand. For example, in response to an add instruction the executionunit performs a simultaneous add operation across each color channelrepresenting a texture element or picture element. By default, theexecution unit performs each instruction across all data channels of theoperands. In some embodiments, instruction control field 712 enablescontrol over certain execution options, such as channels selection(e.g., predication) and data channel order (e.g., swizzle). For 128-bitinstructions 710 an exec-size field 716 limits the number of datachannels that will be executed in parallel. In some embodiments,exec-size field 716 is not available for use in the 64-bit compactinstruction format 730.

Some execution unit instructions have up to three operands including twosource operands, src0 722, src1 722, and one destination 718. In someembodiments, the execution units support dual destination instructions,where one of the destinations is implied. Data manipulation instructionscan have a third source operand (e.g., SRC2 724), where the instructionopcode JJ12 determines the number of source operands. An instruction'slast source operand can be an immediate (e.g., hard-coded) value passedwith the instruction.

In some embodiments instructions are grouped based on opcode bit-fieldsto simplify Opcode decode 740. For an 8-bit opcode, bits 4, 5, and 6allow the execution unit to determine the type of opcode. The preciseopcode grouping shown is merely an example. In some embodiments, a moveand logic opcode group 742 includes data movement and logic instructions(e.g., move (mov), compare (cmp)). In some embodiments, move and logicgroup 742 shares the five most significant bits (MSB), where move (mov)instructions are in the form of 0000xxxxb (e.g., 0x0x) and logicinstructions are in the form of 0001xxxxb (e.g., 0x01). A flow controlinstruction group 744 (e.g., call, jump (jmp)) includes instructions inthe form of 0010xxxxb (e.g., 0x20). A miscellaneous instruction group746 includes a mix of instructions, including synchronizationinstructions (e.g., wait, send) in the form of 0011xxxxb (e.g., 0x30). Aparallel math instruction group 748 includes component-wise arithmeticinstructions (e.g., add, multiply (mul)) in the form of 0100xxxxb (e.g.,0x40). The parallel math group 748 performs the arithmetic operations inparallel across data channels. The vector math group 750 includesarithmetic instructions (e.g., dp4) in the form of 0101xxxxb (e.g.,0x50). The vector math group performs arithmetic such as dot productcalculations on vector operands.

Graphics Pipeline

FIG. 8 is a block diagram of another embodiment of a graphics processor800. Elements of FIG. 8 having the same reference numbers (or names) asthe elements of any other figure herein can operate or function in anymanner similar to that described elsewhere herein, but are not limitedto such.

In some embodiments, graphics processor 800 includes a graphics pipeline820, a media pipeline 830, a display engine 840, thread execution logic850, and a render output pipeline 870. In some embodiments, graphicsprocessor 800 is a graphics processor within a multi-core processingsystem that includes one or more general purpose processing cores. Thegraphics processor is controlled by register writes to one or morecontrol registers (not shown) or via commands issued to graphicsprocessor 800 via a ring interconnect 802. In some embodiments, ringinterconnect 802 couples graphics processor 800 to other processingcomponents, such as other graphics processors or general-purposeprocessors. Commands from ring interconnect 802 are interpreted by acommand streamer 803, which supplies instructions to individualcomponents of graphics pipeline 820 or media pipeline 830.

In some embodiments, command streamer 803 directs the operation of avertex fetcher 805 that reads vertex data from memory and executesvertex-processing commands provided by command streamer 803. In someembodiments, vertex fetcher 805 provides vertex data to a vertex shader807, which performs coordinate space transformation and lightingoperations to each vertex. In some embodiments, vertex fetcher 805 andvertex shader 807 execute vertex-processing instructions by dispatchingexecution threads to execution units 852A, 852B via a thread dispatcher831.

In some embodiments, execution units 852A, 852B are an array of vectorprocessors having an instruction set for performing graphics and mediaoperations. In some embodiments, execution units 852A, 852B have anattached L1 cache 851 that is specific for each array or shared betweenthe arrays. The cache can be configured as a data cache, an instructioncache, or a single cache that is partitioned to contain data andinstructions in different partitions.

In some embodiments, graphics pipeline 820 includes tessellationcomponents to perform hardware-accelerated tessellation of 3D objects.In some embodiments, a programmable hull shader 811 configures thetessellation operations. A programmable domain shader 817 providesback-end evaluation of tessellation output. A tessellator 813 operatesat the direction of hull shader 811 and contains special purpose logicto generate a set of detailed geometric objects based on a coarsegeometric model that is provided as input to graphics pipeline 820. Insome embodiments, if tessellation is not used, tessellation components811, 813, 817 can be bypassed.

In some embodiments, complete geometric objects can be processed by ageometry shader 819 via one or more threads dispatched to executionunits 852A, 852B, or can proceed directly to the clipper 829. In someembodiments, the geometry shader operates on entire geometric objects,rather than vertices or patches of vertices as in previous stages of thegraphics pipeline. If the tessellation is disabled the geometry shader819 receives input from the vertex shader 807. In some embodiments,geometry shader 819 is programmable by a geometry shader program toperform geometry tessellation if the tessellation units are disabled.

Prior to rasterization, vertex data is processed by a clipper 829, whichis either a fixed function clipper or a programmable clipper havingclipping and geometry shader functions. In some embodiments, arasterizer 873 in the render output pipeline 870 dispatches pixelshaders to convert the geometric objects into their per pixelrepresentations. In some embodiments, pixel shader logic is included inthread execution logic 850.

The graphics processor 800 has an interconnect bus, interconnect fabric,or some other interconnect mechanism that allows data and messagepassing amongst the major components of the processor. In someembodiments, execution units 852A, 852B and associated cache(s) 851,texture and media sampler 854, and texture/sampler cache 858interconnect via a data port 856 to perform memory access andcommunicate with render output pipeline components of the processor. Insome embodiments, sampler 854, caches 851, 858 and execution units 852A,852B each have separate memory access paths.

In some embodiments, render output pipeline 870 contains a rasterizerand depth test component 873 that converts vertex-based objects intotheir associated pixel-based representation. In some embodiments, therasterizer logic includes a windower/masker unit to perform fixedfunction triangle and line rasterization. Associated render and depthbuffer caches 878, 879 are also available in some embodiments. A pixeloperations component 877 performs pixel-based operations on the data,though in some instances, pixel operations associated with 2D operations(e.g. bit block image transfers with blending) are performed by the 2Dengine 841, or substituted at display time by the display controller 843using overlay display planes. In some embodiments, a shared L3 cache 875is available to all graphics components, allowing the sharing of datawithout the use of main system memory.

In some embodiments, graphics processor media pipeline 830 includes amedia engine 337 and a video front end 834. In some embodiments, videofront end 834 receives pipeline commands from the command streamer 803.In some embodiment media pipeline 830 includes a separate commandstreamer. In some embodiments, video front-end 834 processes mediacommands before sending the command to the media engine 837. In someembodiments, media engine 337 includes thread spawning functionality tospawn threads for dispatch to thread execution logic 850 via threaddispatcher 831.

In some embodiments, graphics processor 800 includes a display engine840. In some embodiments, display engine 840 is external to processor800 and couples with the graphics processor via the ring interconnect802, or some other interconnect bus or fabric. In some embodiments,display engine 840 includes a 2D engine 841 and a display controller843. In some embodiments, display engine 840 contains special purposelogic capable of operating independently of the 3D pipeline. In someembodiments, display controller 843 couples with a display device (notshown), which may be a system integrated display device, as in a laptopcomputer, or an external display device attached via a display deviceconnector.

In some embodiments, graphics pipeline 820 and media pipeline 830 areconfigurable to perform operations based on multiple graphics and mediaprogramming interfaces and are not specific to any one applicationprogramming interface (API). In some embodiments, driver software forthe graphics processor translates API calls that are specific to aparticular graphics or media library into commands that can be processedby the graphics processor. In some embodiments, support is provided forthe Open Graphics Library (OpenGL) and Open Computing Language (OpenCL)from the Khronos Group, the Direct3D library from the MicrosoftCorporation, or support may be provided to both OpenGL and D3D. Supportmay also be provided for the Open Source Computer Vision Library(OpenCV). A future API with a compatible 3D pipeline would also besupported if a mapping can be made from the pipeline of the future APIto the pipeline of the graphics processor.

Graphics Pipeline Programming

FIG. 9A is a block diagram illustrating a graphics processor commandformat 900 according to some embodiments. FIG. 9B is a block diagramillustrating a graphics processor command sequence 910 according to anembodiment. The solid lined boxes in FIG. 9A illustrate the componentsthat are generally included in a graphics command while the dashed linesinclude components that are optional or that are only included in asub-set of the graphics commands The exemplary graphics processorcommand format 900 of FIG. 9A includes data fields to identify a targetclient 902 of the command, a command operation code (opcode) 904, andthe relevant data 906 for the command A sub-opcode 905 and a commandsize 908 are also included in some commands

In some embodiments, client 902 specifies the client unit of thegraphics device that processes the command data. In some embodiments, agraphics processor command parser examines the client field of eachcommand to condition the further processing of the command and route thecommand data to the appropriate client unit. In some embodiments, thegraphics processor client units include a memory interface unit, arender unit, a 2D unit, a 3D unit, and a media unit. Each client unithas a corresponding processing pipeline that processes the commands Oncethe command is received by the client unit, the client unit reads theopcode 904 and, if present, sub-opcode 905 to determine the operation toperform. The client unit performs the command using information in datafield 906. For some commands an explicit command size 908 is expected tospecify the size of the command In some embodiments, the command parserautomatically determines the size of at least some of the commands basedon the command opcode. In some embodiments commands are aligned viamultiples of a double word.

The flow diagram in FIG. 9B shows an exemplary command sequence 910. Insome embodiments, software or firmware of a data processing system thatfeatures an embodiment of a graphics processor uses a version of thecommand sequence shown to set up, execute, and terminate a set ofgraphics operations. A sample command sequence is shown and describedfor purposes of example only as embodiments are not limited to thesespecific commands or to this command sequence. Moreover, the commandsmay be issued as batch of commands in a command sequence, such that thegraphics processor will process the sequence of commands in at leastpartially concurrence.

In some embodiments, sample command sequence 910 may begin with apipeline flush command 912 to cause any active graphics pipeline tocomplete the currently pending commands for the pipeline. In someembodiments, the 3D pipeline 922 and the media pipeline 924 do notoperate concurrently. The pipeline flush is performed to cause theactive graphics pipeline to complete any pending commands In response toa pipeline flush, the command parser for the graphics processor willpause command processing until the active drawing engines completepending operations and the relevant read caches are invalidated.Optionally, any data in the render cache that is marked ‘dirty’ can beflushed to memory. In some embodiments, pipeline flush command 912 canbe used for pipeline synchronization or before placing the graphicsprocessor into a low power state.

In some embodiments, a pipeline select command 913 is used when acommand sequence requires the graphics processor to explicitly switchbetween pipelines. In some embodiments, a pipeline select command 913 isrequired only once within an execution context before issuing pipelinecommands unless the context is to issue commands for both pipelines. Insome embodiments, a pipeline flush command is 912 is requiredimmediately before a pipeline switch via the pipeline select command913.

In some embodiments, a pipeline control command 914 configures agraphics pipeline for operation and is used to program the 3D pipeline922 and the media pipeline 924. In some embodiments, pipeline controlcommand 914 configures the pipeline state for the active pipeline. Inone embodiment, the pipeline control command 914 is used for pipelinesynchronization and to clear data from one or more cache memories withinthe active pipeline before processing a batch of commands

In some embodiments, return buffer state commands 916 are used toconfigure a set of return buffers for the respective pipelines to writedata. Some pipeline operations require the allocation, selection, orconfiguration of one or more return buffers into which the operationswrite intermediate data during processing. In some embodiments, thegraphics processor also uses one or more return buffers to store outputdata and to perform cross thread communication. In some embodiments, thereturn buffer state 916 includes selecting the size and number of returnbuffers to use for a set of pipeline operations.

The remaining commands in the command sequence differ based on theactive pipeline for operations. Based on a pipeline determination 920,the command sequence is tailored to the 3D pipeline 922 beginning withthe 3D pipeline state 930, or the media pipeline 924 beginning at themedia pipeline state 940.

The commands for the 3D pipeline state 930 include 3D state settingcommands for vertex buffer state, vertex element state, constant colorstate, depth buffer state, and other state variables that are to beconfigured before 3D primitive commands are processed. The values ofthese commands are determined at least in part based the particular 3DAPI in use. In some embodiments, 3D pipeline state 930 commands are alsoable to selectively disable or bypass certain pipeline elements if thoseelements will not be used.

In some embodiments, 3D primitive 932 command is used to submit 3Dprimitives to be processed by the 3D pipeline. Commands and associatedparameters that are passed to the graphics processor via the 3Dprimitive 932 command are forwarded to the vertex fetch function in thegraphics pipeline. The vertex fetch function uses the 3D primitive 932command data to generate vertex data structures. The vertex datastructures are stored in one or more return buffers. In someembodiments, 3D primitive 932 command is used to perform vertexoperations on 3D primitives via vertex shaders. To process vertexshaders, 3D pipeline 922 dispatches shader execution threads to graphicsprocessor execution units.

In some embodiments, 3D pipeline 922 is triggered via an execute 934command or event. In some embodiments, a register write triggers commandexecution. In some embodiments execution is triggered via a ‘go’ or‘kick’ command in the command sequence. In one embodiment commandexecution is triggered using a pipeline synchronization command to flushthe command sequence through the graphics pipeline. The 3D pipeline willperform geometry processing for the 3D primitives. Once operations arecomplete, the resulting geometric objects are rasterized and the pixelengine colors the resulting pixels. Additional commands to control pixelshading and pixel back end operations may also be included for thoseoperations.

In some embodiments, sample command sequence 910 follows the mediapipeline 924 path when performing media operations. In general, thespecific use and manner of programming for the media pipeline 924depends on the media or compute operations to be performed. Specificmedia decode operations may be offloaded to the media pipeline duringmedia decode. In some embodiments, the media pipeline can also bebypassed and media decode can be performed in whole or in part usingresources provided by one or more general purpose processing cores. Inone embodiment, the media pipeline also includes elements forgeneral-purpose graphics processor unit (GPGPU) operations, where thegraphics processor is used to perform SIMD vector operations usingcomputational shader programs that are not explicitly related to therendering of graphics primitives.

In some embodiments, media pipeline 924 is configured in a similarmanner as the 3D pipeline 922. A set of media pipeline state commands940 are dispatched or placed into in a command queue before the mediaobject commands 942. In some embodiments, media pipeline state commands940 include data to configure the media pipeline elements that will beused to process the media objects. This includes data to configure thevideo decode and video encode logic within the media pipeline, such asencode or decode format. In some embodiments, media pipeline statecommands 940 also support the use one or more pointers to “indirect”state elements that contain a batch of state settings.

In some embodiments, media object commands 942 supply pointers to mediaobjects for processing by the media pipeline. The media objects includememory buffers containing video data to be processed. In someembodiments, all media pipeline states must be valid before issuing amedia object command 942. Once the pipeline state is configured andmedia object commands 942 are queued, the media pipeline 924 istriggered via an execute command 934 or an equivalent execute event(e.g., register write). Output from media pipeline 924 may then be postprocessed by operations provided by the 3D pipeline 922 or the mediapipeline 924. In some embodiments, GPGPU operations are configured andexecuted in a similar manner as media operations.

Graphics Software Architecture

FIG. 10 illustrates exemplary graphics software architecture 1000 for adata processing system, according to some embodiments. Softwarearchitecture includes a 3D graphics application 1010, an operatingsystem 1020, and at least one processor 1030. In some embodiments,processor 1030 includes a graphics processor 1032 and one or moregeneral-purpose processor core(s) 1034. The graphics application 1010and operating system 1020 each execute in the system memory 1050 of thedata processing system.

In some embodiments, 3D graphics application 1010 contains one or moreshader programs including shader instructions 1012. The shader languageinstructions may be in a high-level shader language, such as the HighLevel Shader Language (HLSL) or the OpenGL Shader Language (GLSL). Theapplication also includes executable instructions 1014 in a machinelanguage suitable for execution by the general-purpose processor core1034. The application also includes graphics objects 1016 defined byvertex data.

In some embodiments, operating system 1020 is a Microsoft® Windows®operating system from the Microsoft Corporation, a proprietary UNIX-likeoperating system, or an open source UNIX-like operating system using avariant of the Linux kernel. When the Direct3D API is in use, theoperating system 1020 uses a front-end shader compiler 1024 to compileany shader instructions 1012 in HLSL into a lower-level shader language.The compilation may be a just-in-time (JIT) compilation or theapplication can perform shader pre-compilation. In some embodiments,high-level shaders are compiled into low-level shaders during thecompilation of the 3D graphics application 1010.

In some embodiments, user mode graphics driver 1026 contains a back-endshader compiler 1027 to convert the shader instructions 1012 into ahardware specific representation. When the OpenGL API is in use, shaderinstructions 1012 in the GLSL high-level language are passed to a usermode graphics driver 1026 for compilation. In some embodiments, usermode graphics driver 1026 uses operating system kernel mode functions1028 to communicate with a kernel mode graphics driver 1029. In someembodiments, kernel mode graphics driver 1029 communicates with graphicsprocessor 1032 to dispatch commands and instructions.

Graphics Processor Power Management Contexts

FIG. 11 is a block diagram illustrating a graphics processor powermanagement architecture 1100, in accordance with some embodiments.Architecture 1100 includes a central processor (CP) 1140, memory 1150,and graphics processor 1180. Central processor 1140, memory 1150, andgraphics processor 1180 may each have any of the attributes describedabove in the context of FIG. 1-10. In one exemplary embodiment, centralprocessor 1140, memory 1150, and graphics processor 1180 are allcomponents on a single chip (system-on-chip, or SoC).

Central processor 1140 includes logic to execute and/or instantiate oneor more applications 1110-1111, for example within a user space managedby an operating system 1108 executing within a kernel space of centralprocessor 1140. Each of user applications 1110-1111 may generatedistinct graphics workloads 1141, 1142 that are to be processed bygraphics processor 1180. For example, a 3D game application may generaterendering workloads and/or compute workloads, a media player or cameracontroller application may generate media processing workloads and/orcodec workloads, etc. The number of different types or classes ofworkloads sent to a graphics processor is dependent on the componentcapabilities of the graphics processor and the application developer.For example, graphics processors with a codec (encoder/decoder) blockmay be expected to receive codec-related workloads if an applicationdeveloper elects to utilize that capability. Central processor 1140might otherwise process such workloads, for example if graphicsprocessor 1180 lacked a codec block. In addition to distinct workloadtypes, applications can generate workloads at differing rates.Application 1110 may issue relatively few rendering workloads, forexample in the case of a word processor application, or a great many, inthe case of the 3D game for example.

In some embodiments, multiple user applications generate graphicsworkloads concurrently. For example, where OS 1108 provides amulti-tasking environment, applications 1110, 1111 may submit workloads1141 and 1142 at substantially the same time. In a multi-display mode,for example, both workloads 1141 and 1142 may be entail rendering.Application workloads 1141, 1142 output to graphics processor 1180(e.g., via driver 1109) are scheduled onto graphics processor resources1170. Graphics processor resources 1170 include one or more resources,such as, but not limited to, execution units, media blocks, renderingpipelines, and encoder/decoder blocks. Each graphics processor resourcemay have any of the attributes described above in the context of FIG.1-10. In the illustrated embodiment, scheduler logic 1160 is toarbitrate between received workloads and schedule their processing ongraphics processor resources 1170. In some embodiments, scheduler logic1160 is to perform time-slicing of graphics processor resources 1170 toprocess concurrently submitted workloads 1141, 1142 as consecutivelyscheduled workloads 1166 dispatched to various graphics processorresources 1170, which in-turn output workload results 1171. Schedulerlogic may include software and/or hardware components. In someembodiments, scheduler logic 1160 is implemented by an OS executing on acentral processor. For such embodiments, the OS may execute one or morecoded workload scheduling algorithms and employ a kernel mode driver(KMD) to pass scheduled workloads to a graphics processor. For theembodiments illustrated in FIG. 11 however, scheduler logic 1160 isimplemented by a microcontroller component of graphics processor 1180.The microcontroller (not depicted) may have any suitable internalmicro-architecture, such as, but not limited to, an x86 architecture.The microcontroller is to receive workloads 1141, 1142, execute codecomprising one or more scheduling algorithms, and output the scheduledworkloads 1166 to one or more graphics processor resources 1170. In someembodiments, workload-scheduling code executed by the microcontroller isstored as firmware on graphics processor 1180.

In some embodiments, graphics processor resource configurationinformation and/or power management state information is stored tomemory in association with a particular application. For example,graphics processor resource configuration and/or power management stateinformation associated with workloads generated by application N may bestored in memory 1150 to a graphics processor context M. One or moregraphics processor context may be stored for a given application. Forexample, graphics processor contexts 1120, 1121, and 1122 may be storedin association with application 1110, while contexts 1130, 1131 arestored to memory in association with application 1111.

In some embodiments, information stored in a graphics processor contextis employed for switching the configuration of graphics processorresources as the resources process various different applicationworkloads. As illustrated in FIG. 11, in addition to outputtingscheduled workloads 1166, scheduler logic 1160 is to output to graphicsprocessor resources 1170 one or more graphics processor contextualcontrol parameters 1165 associated with the particular workload beingscheduled. Scheduler logic 1160 is communicatively coupled to memory1150 to access graphic processor context data 1134 stored in associationwith a particular graphic processor context. Graphics processor resourceconfiguration may be switched based on parameters stored in a particularcontext that is associated with the workload and communicatedconcurrently with the workload. For example, in some embodiments aportion of commands streamed to a hardware resource specifyconfiguration parameters accessed from the stored graphics processorcontext data structure.

FIG. 12 is a flow chart illustrating a graphics processor powermanagement method 1201 employing a graphics processor context, inaccordance with some embodiments. Graphics processor 1180 (FIG. 11) mayperform method 1201, for example. At operation 1210, graphics processorcontexts, each a data structure including information indicative of ahardware configuration for one or more graphics processor resources, arecreated and stored to memory. At operation 1220, data stored in thegraphics processor context is used to load the appropriate resourceconfiguration when the workload scheduled to a graphics processorresource is executed by the resource. Context switching operation 1220is to ensure that a predetermined power-performance configuration is setimmediately as a scheduled workload begins running on the one or moregraphics processor resources. At operation 1230, information associatedwith a graphics processor context is updated, for example based onperformance data generated by the hardware resource that processed aworkload while in that context. As described further below, contextupdate operation 1230 is to maintain historical state information acrossexecution of multiple concurrent workloads that enables power managementalgorithms to operate at the granularity of specific applications'graphics processor workload.

In some embodiments, a graphics processor context is associated withinformation indicative of at least a power state or an operatingfrequency of one or more graphics processor resource. In someembodiments, power state information specifies a power-gatingconfiguration that powers-up or powers-down various sub-components ofthe graphics processor resources. In some embodiments, a graphicsprocessor context is associated with information indicative of both apower state and an operating frequency of one or more graphics processorresource. In some embodiments, a graphics processor context isassociated with information indicative of operating frequencies externalto the graphics processor resources and/or graphics processor. Forexample, a graphics processor context may include information indicativeof SoC component operating frequencies that are to be programmed when aparticular context is switched-in and starts executing on the graphicsprocessor resource(s). In some embodiments, a graphics processor contextis associated with information indicative of power management stateinformation that customizes power-management algorithms for apower-performance profile of the particular context.

FIG. 13A further illustrates a graphics processor context 1120, storedin an electronic memory in accordance with some embodiments. In someembodiments, a graphics processor context comprises a data structureincluding a power gating (P_Gate) configuration control parameter. Insome embodiments, a power gating configuration control includesparameters indicative of power states for one or more of a slice,sub-slice, execution unit, encoder/decoder block, or media block of agraphics processor. P_Gate control vector 1305, for example, specifiessub-slice and/or EU i-j to be powered up (“on”). P_Gate control vector1305 further specifies a codec block of the graphics processor to bepowered down (“off”). P_Gate control vector 1305 further specifies amedia block of the graphics processor to be powered down (“off”). Insome embodiments these power states are associated with on/off statesfor various corresponding power gate transistors controlling powerdistribution to predetermined graphics processor resources.

In some embodiments, a graphics processor context comprises a datastructure further including a component operating frequency controlparameter. Operating frequency control parameters stored to context 1120may be specified for one or more graphics processor resource (e.g.,graphics processor operating frequency target f_(GP,Req)). Operatingfrequency control parameters stored to context 1120 may be indicative ofoperating frequencies external to graphics processor resources and/orgraphics processor. For example, component operating frequency controlvector 1310 includes a parameter for a central processor maximumoperating frequency f_(CP,Cap) that may be utilized by a controller of acentral processor resource to coordinate central processorpower-performance control with control efforts being applied at thecontext-level within the graphics processor. Component operatingfrequency control vector 1310 may include other SoC operating parametersas well, such as a target central processor operating frequencyf_(CP,Req) affecting the balance of power between central processor(s)and graphics processor(s).

In some embodiments, a graphics processor context comprises a datastructure further including power management state information. Powermanagement state information specifies at least one of managementalgorithms, performance metrics, or performance targets. A performancemanagement algorithm may specify how to manage a hardware resource'sperformance while the graphics processor context is in effect. Forexample, the performance management algorithm may manage performance tomaximize a performance target of one or more powered-up hardwareresource, and/or reach a target idleness (busyness) of one or morepowered-up hardware resource. Power management state information storedin association with a graphics processor context may further includevarious performance characterizations made based on performance dataoutput by one or more graphics processor resources while operating inthe particular context. For example, power management state informationmay include statistical descriptors of graphics processor resourceperformance associated with a particular context.

In some embodiments, performance data and resulting characterizationinformation is incrementally stored in the graphics processor contextwith each workload processed while the context was active. Examples ofperformance characterizing data include, but are not limited to,workload flip-rate, display refresh rate, and resource idleness(busyness). Power management state information stored in associationwith a context may further include context performance targets, such as,but not limited to, a maximum frame-rate (e.g., fps.). A frame-ratetarget may be specified by an application or otherwise (e.g., throughgraphics driver management setting). Power management algorithms cantherefore utilize the power management state information to exert eithercontext-level or global control efforts, for example to achievecompatible frame-rates between applications. In the illustrated example,power management state information 1320 includes a centralprocessor-graphics processor multiplier specifying a target operatingfrequency ratio to maintain between central processor resource(s) andgraphics processor resource(s). Power management state information 1320further includes a duty cycle control (DCC) performance targetcontrolling a deep sleep state (rC6) duration. The DCC performancetarget may specify idleness for one or more graphics processor resourcesto achieve an overall improvement in graphics processor power efficiencyand greater performance for active resources while under power-limitedsituations.

FIG. 13B illustrates a graphics processor context lifecycle 1301 as agraphics processor power management method is performed, in accordancewith some embodiments. At the various stages illustrated, a givengraphics processor context is operated upon, beginning with creationoperation 1330 performed in response to launching of a user application.Creation operation 1330 may, for example, occur during operation 1210(FIG. 12) to associate a particular context with a particularapplication workload. Context creation may be triggered when anapplication opens a connection to the graphics processor through thegraphics driver API. For example, a first rendering context may becreated at operation 1330 in response to a first application opening arendering connection to the graphics processor. Alternatively, a computecontext may be created in response to an application opening a computeconnection to the graphics processor. Likewise, a second renderingcontext may be created at operation 1330 in response to a secondapplication opening a rendering connection to the graphics processor,and so on. A user application and/or graphics processor driver may setsome or all graphics processor context information at creation operation1330. For example, a graphics processor context for a media playerapplication may have a predetermined optimal graphics processorconfiguration to run any media workloads. These values are then to bestored in the graphics processor context associated with thatapplication. In another example, an application may specify workloads ofa context are to run at a maximum graphics processor operatingfrequency, or maximum frame-rate, etc.

Subsequent to context creation, the graphics processor context isemployed a first time to process a first workload. Based on datacollected during this first use, a performance profile for the contextis characterized at context evaluation operation 1340. The performanceprofile may then be utilized to determine one or more performancemetrics that are to be targeted by a power management algorithm for theparticular context. The resulting characterization is to be stored backinto the associated graphics processor context data structure, updatingthe context information at the end of some predetermined evaluationperiod (e.g., 100's-1000's of milliseconds).

In some embodiments, the context performance profile characterization isperformed by power management logic responsible for implementing powermanagement algorithms. For example, in further reference to FIG. 11,power management logic 1190 is communicatively coupled to memory 1150and is to access and/or store contextual performance profile data 1137.In some embodiments, the same microcontroller executing workloadscheduling code to implement scheduler logic 1160 also executes powermanagement code to implement power management logic 1190. Alternatively,a graphics driver, for example executing in kernel mode on centralprocessor 1140, may implement power management logic 1190.

Returning to FIG. 13B, once a context has been created and initiallyevaluated, the context information is accessed during switch-inoperation 1350. In some embodiments, switching-in is triggered upon ascheduler determining to execute a workload on the graphics processorresources. Changes to the configuration of one or more graphicsprocessor resources at operation 1350 are based on data stored in thegraphics processor context. Such data may have originated from any ofthe creation operation 1330, evaluation operation 1340, or one or moreprior executions of workloads submitted under this same context. Any ofthe power-gating configuration information, component frequencyinformation, or power management state information introduced inreference to FIG. 13A may be applied at operation context switchoperation 1350.

At operation 1360, the graphics processor context is switched out.Operation 1360 may be triggered by a graphics processor resourcecompletely a workload or by a workload scheduler pre-emptively switchingto another context. Stored information associated with the graphicsprocessor context may be updated at operation 1360. For example,additional management algorithm state information associated with thegraphics processor context may be written out to the context datastructure at the context switch out operation 1360. Such historicalinformation may then be utilized when the same context is subsequentlyswitched back in at operation 1350. Graphics processor power-gatingconfiguration parameters may also be updated at the switch-out operation1360, for example based on statistics collected during the execution ofone or more workloads within this context over some graphics processortime slice(s).

Updates to power-gating configuration parameters may enable workloadsassociated with a particular context to execute more efficiently whenthe context is subsequently switched back in at operation 1350.Performance statistics may be based on performance data output by thegraphics processor resources along with the workload processing results.Workload results are returned to the originating application, and theassociated performance data may be written out to memory in associationwith the graphics processor context (e.g., written to the context datastructure). Notably, the overhead associated with switching in controlparameters of a particular context may be very little. For example,power-gating and operating frequency changes may be implemented in a fewnanoseconds, or less. Hence, operations 1350 and 1360 may be performedin lock-step with workload processing without incurring a significantlatency penalty. The final context operation illustrated in FIG. 13B isdeletion operation 1370, where all stored context information is lost.Operation 1370 may be performed in response to an application closing aconnection to the graphics processor (e.g., when a user application isclosed).

With the above power-management architecture, performance profiling toeach application workload is partitioned, enabling an optimalconfiguration (e.g., power-gating setup, operating frequency) to beselected for each application. Graphics processor configuration changesmay be made immediately when a given application starts executing workon the graphics processor. Hence, the above power-managementarchitecture is able to be more responsive to individual workload needs,meeting those needs more efficiently than is possible for architectureslimited to longer control intervals that reflect requirements of manydisparate workloads.

Referring back to the exemplary architecture illustrated in FIG. 11,context-specific performance targets may be processed by powermanagement logic 1190 based on resource performance data 1172 output bygraphics processor resources 1170. Performance data 1172 may be outputcontemporaneously with workload results 1171 such that performance data1172 is attributable to the particular hardware configuration,power-management algorithm(s), and power-management state(s) in effectwhen the workload was processed. Performance data 1172 may therefore beassociated with a particular graphics processor context and powermanagement logic 1190 may process performance data 1172 to outputcontextual performance profile data 1137 that may be stored inassociation with corresponding graphics processor contexts 1120-1137.

In some embodiments, a power-management architecture is further basedglobal performance targets. Global performance targets may be trackedand utilized in one or more power-management algorithms to controlgraphics processor hardware in a manner that supplements or augmentsapplication-specific context-level management. As used herein, a globalperformance target is associated with a metric that is evaluated over aninterval that exceeds the switch-in and switch-out times of graphicsprocessor contexts currently executing. For example, centralprocessor/graphics processor operating frequency multiplier targets andDCC control targets may be advantageously modified over relatively long(e.g., millisecond) evaluation intervals. Because of the longerevaluation interval, global performance targets are not mapped uniquelyto a single context. In the exemplary architecture illustrated in FIG.11, power management logic 1190 may process graphics performance data1172 to generate global performance profile data 1139 for the purpose ofglobal power-management. In the illustrated example, global performanceprofile data 1139 includes global performance targets 1135 stored tomemory 1150.

When multiple graphics processor contexts are executing workloads andswitching in and out, power management logic 1190 is advantageouslyconfigured to execute power-management algorithms based either oncontext performance targets or global performance targets. Acontext-specific frame-rate target is an example of a contextualperformance target while a single frame-rate target for all workloads isan example of a global performance target. In a use case where differentregions of a display area are rendered for different applications (e.g.,application GUI windows), each application may be sending workloadsprocessed under an associated rendering context. Those contexts, mightspecify, for example, unique workload frame-rate targets (e.g., a 30 FPStarget for camera image data workloads, and 120 FPS target for 3D gamerendering workloads). Under each context then, respective scenes wouldbe rendered into an off-screen memory buffer, which is then drawn at therefresh rate of the screen (e.g., 60 Hz). Under such circumstances, aglobal performance target relating to a visual quality metric, such asthe screen refresh rate, is then applied across all renderingapplications.

FIG. 14 is a flow diagram illustrating a power-performance managementmethod 1401 that is based either on global or context-specific graphicsprocessor performance targets, in accordance with some embodiments.Method 1401 begins with collecting graphics performance data over apredetermined global performance target evaluation interval. Atoperation 1405, the dominant graphics processor context for theevaluation interval is identified. In some embodiments, the dominantgraphics processor context is the context that consumes the greatestproportion of graphics processor resource time within the evaluationinterval. In further embodiments, time slices associated with graphicsprocessing under the dominant context are accumulated and compared to apredetermined threshold. If the dominant context processing timesatisfies the threshold, method 1401 proceeds to operation 1410 whereone or more power-performance management algorithms are implementedbased on the context-specific performance targets associated with thedominant graphics processor context. The dominant context is thereforeassumed to be responsible for the global performance targets.

If instead, the dominant context processing time fails to satisfy thethreshold, the context is not deemed responsible for the globalperformance targets and method 1401 proceeds to operation 1415. Tomaintain the global performance target, power-performance managementalgorithms are implemented at operation 1415 using global performancemetrics collected during the evaluation interval independent of graphicsprocessor context. Global performance metrics may, for example, comprisegraphics processor performance data averaged over all workloadsprocessed during the evaluation interval, rather than only a subset ofthose associated with a dominant context. For each evaluation interval,one or more graphics processor resource control parameter is updated atoperation 1420. The graphics processor hardware is then configured atoperation 1430 based on those parameters. Method 1401 is then iteratedonce for each subsequent evaluation interval.

In some embodiments, context-level control over one or more graphicsprocessor resource is selectable, providing multiple graphics processorresource control modes. In a first mode, graphics processor resourceconfigurations are switched as a function of the workload, for exampleas described above. In a second mode, context-level control is disabledleaving graphics processor configuration control dependent on globalperformance targets. Referring again to the exemplary architectureillustrated in FIG. 11, power management logic 1190 is furtherconfigured to assess the workloads being processed and determine ifscheduler logic 1160 is to implement context switching of graphicsprocessor resources 1170. In the exemplary embodiment, power managementlogic 1190 is to generate a graphics processor control mode indicator1191 that is communicated to scheduler logic 1160. Graphics processorcontrol mode indicator 1191 may be a context control enable/disable flagbit, for example. Scheduler logic 1160 is then to be responsive to thecontrol mode indicator 1191, either outputting contextual control 1165,or not. In absence of contextual control 1165, graphics processorresources 1170 may be configured and operated based on controlparameters 1192 output by power management logic 1190, for example basedon power management algorithms using global performance targets.

FIG. 15 is a block diagram further illustrating power management andworkload scheduling on graphics processor resources, in accordance withsome embodiments. In this architecture, power management logic 1190 isto execute a performance evaluation loop 1450 that includes selectingbetween global and context-level control of one or more graphicsprocessor resource at operation 1455. In response to control mode flag1191 output by power management logic 1190, scheduler logic 1160implements context-based control 1506, or not, in conjunction witharbitration of workloads to graphics processor resources. Hence,scheduler logic 1160 may in a first mode perform only workloadarbitration 1505, and in a second mode perform both workload arbitration1505 along with context-based control 1506.

Without context-level control, power management logic 1190 exerts aglobal control effort on the one or more graphics processor resources atoperation 1460 during the subsequent evaluation interval. In someembodiments, the control mode is based on a total number of differentcontexts switched in during the predetermined evaluation interval. Ifthat number satisfies a predetermined threshold, for example, thenglobal control may be selected for the subsequent performance evaluationinterval. Although contexts may switch 500-1000 times/second, or more,switches may be between only a few different contexts (e.g., 1-3). Thus,a particular context may switch in and out many times during anevaluation interval that may be 50-100 milliseconds, for example. Insuch a situation, context-level control may provide significantadvantageous over global control. However, when many (e.g., 10 or more)different contexts are switching-in, global control algorithms thataverage over the many contexts may be more advantageous. In alternativeembodiments, context switching during the subsequent performanceevaluation interval may be contingent on identifying a sufficientlydominant context. For example, context control may be enabled if thereis a dominant context, and disabled if there is not sufficientlydominant context.

Phased Graphics Processor Power-Performance Management

In some embodiments, graphics processor power management is performed instages or phases. Power-performance management algorithms grouped intoseparate phases may be performed sequentially (phase-by-phase) to arriveat one or more final control parameters. Ordering the algorithmsaccording to phases allows for potentially numerous managementalgorithms while maintaining algorithm independence so that each may beseparately optimized. With the framework described in accordance withsome embodiments herein, an algorithm hierarchy is established through atemporal sequencing of the management algorithm processing. In someembodiments, each phase is associated with one or more specific powermanagement algorithms In some embodiments, subsequent power-performancemanagement phases may override control parameters values applied by anearlier phase. In other words, control parameter values determined byany algorithms executed first in time as part of a precedent phase arecandidates for being modified by any algorithms executed second in timeas part of a subsequent phase. Algorithms that may generate conflictingcontrol parameter values are therefore to be separated into differentphases, with any in the later stage having priority. This hierarchicalmanagement structure is one of the driving factors for the exemplarysequential ordering of algorithms described for one or more embodimentherein. Another driving factor is dependency of one management algorithmon the control made during the previous phase. Hence, sequentialmanagement algorithm ordering should reflect both algorithm dependencyand a hierarchical management structure.

Once all phase are completed and all potential control parametermodifications made, a finalized set of control parameter values(requests) may be output to configure hardware associated with one ormore graphics processor resource. The graphics processor powermanagement phases may then be repeated to arrive at another set ofcontrol parameter values based on more recent graphics processorperformance data.

FIG. 16 is a flow diagram illustrating a phased graphics processor powermanagement method 1601 employing a sequential control loop, inaccordance with some embodiments, in accordance with some embodiments.Method 1601 begins at operation 1605 where a trigger initiates thecontrol loop. In some embodiments, the control loop is initiated basedon a passage of a predetermined time (e.g., loop is executed with afixed period). The predetermined time for example may be based on aspecific evaluation interval over which performance data is to becollected. In some embodiments, method 1601 is initiated at a fixedperiod of 100 milliseconds, or more. Relative to the rate at whichworkloads are processed (and contexts may be switched), method 1601 maythen be considered a slow loop. Depending on the resources allocated toexecuting method 1601, the loop may be initiated more frequently (e.g.,every 10 ms, or less). In some other embodiments, method 1601 isinitiated based on one or more trigger events. Once initiated, method1601 proceeds to operation 1615 where a set of graphics processorhardware configuration parameters is sequentially determined following apredetermined order. At operation 1625 the set of parameters areassembled into an output signal (e.g., a control parameter vector)communicated as requests to the graphics processor resources.

FIG. 17 is a block diagram further illustrating a phased graphicsprocessor power management architecture employing a sequential controlloop, in accordance with some embodiments.). In some exemplaryembodiments, central processor 1140, memory 1150, and graphics processorresources 1170 are all components on a single chip (SoC 1799). Themanagement structure illustrated in FIG. 17 may be practiced independentof contextual power-performance control of graphics processor resources,or it may be utilized to in conjunction with contextualpower-performance control. In one embodiment, a sequential powermanagement control loop is implemented in conjunction withcontext-specific control parameters to generate control parameter valueupdates to the graphics processor context information. In anotherembodiment, a sequential power management control loop generates a setof control parameters output as a global control effort in the absenceof any context-specific control. In some embodiments, a sequential powermanagement control loop generates a set of control parameters thatincludes both global control parameters and context-specific controlparameters. Hence, some global control parameters (e.g., DCC) may begenerated even if context-specific control parameters (e.g., definingthe number of powered slices and/or EUs, and there associated operatingfrequency) are also generated. In still other embodiments, a sequentialpower management control loop generates a set of control parameters thatincludes one or more control parameter that may be eithercontext-specific, or global (e.g., where management algorithms areswitchable between global or context level performance targets.)

Power management logic 1190 is configured to sequentially performvarious control phases, each of which is associated with one or moregraphics processor power-performance management algorithm and generatesone or more control parameter value. In some embodiments, powermanagement logic 1190 is to perform each phase, one after the other,during a control loop iteration executed once for each performanceevaluation interval. Graphics processor performance data 1172 collectedduring a given evaluation interval is queued in a FIFO buffer 1790 forinput into algorithms in one or more of the management phases. All datain the buffer may be processed together during a single pass through apower management phase to generate one or more parameters values of acontrol vector 1705 to be output at operation 1750.

In some embodiments where graphics processor contexts are switching withworkload, the management phases illustrated in FIG. 17 may be furtherpartitioned between contexts, such that control vector 1705 is acontext-specific control vector generated for each context evaluatedduring one particular power management evaluation interval. For suchembodiments, control vector 1705 contains information for updating theassociated graphics processor context data stored in memory. Forexample, where three contexts have switched in and out during anevaluation interval, each management phase illustrated in FIG. 17 maygenerate three independent control parameter sets, output as threecontrol vectors 1705 written out to update three different graphicsprocessor contexts. Furthermore, where a context has switched in and outN times over an evaluation interval, FIFO buffer 1790 may queueperformance data 1172 generated during each of N runs associated withgraphics processor time slices for the relevant context. All thecontext-specific data collected over the evaluation interval may then beprocessed in the current management loop iteration to arrive at controlparameter values.

In some embodiments, subsequent power-performance management phases mayoverride control parameters values applied by an earlier phase. Thishierarchical management structure is one of the driving factors for theexemplary sequential ordering of algorithms described for one or moreembodiment herein. Another driving factor is dependency of onemanagement algorithm on the control made during the previous phase.Hence, sequential management algorithm ordering should reflect both ahierarchical algorithm dependency and a hierarchical managementstructure.

In some embodiments, during a first phase power management logic 1190 isto evaluate the graphics processor configuration needed to process oneor more new workloads at operation 1710. In some embodiments, theminimum graphics processor resources needed to process a new workload1701 is determined. By minimizing the active components during thisfirst phase, a greater energy budget may be liberated to run the minimumresource set faster (e.g., at a high operating frequency). Thealgorithms processed during operation 1710 output an initial power gateconfiguration 1305 for at least the graphics processor resources 1170.The configuration settings are stored to memory 1150, for example, asone or more control parameter values in control vector 1705. Theconfiguration settings may also be provided as an input to subsequentpower management control phases.

In some embodiments, during a subsequent second phase, power managementlogic 1190 is to execute one or more power-performance algorithm tocharacterize performance metrics for one or more workloads in process(WIP) 1715, and determine performance targets at operation 1720.Exemplary performance metrics include any of those introduced above(e.g., workload flip-rate, display refresh-rate, and resource idleness).Targets, such as a maximum workload frame-rate that can be achieved inthe current platform environment (battery life, chip temperature, OSpower-plan setting, etc.) are determined for the chosen performancemetrics. The performance targets are output to populate additionalfields of control vector 1705, and/or modify one or more power gatingconfiguration values set during the first phase. Power gatingconfiguration values may be modified for example when the performancecharacterization indicates the power gating configuration values setduring the first phase are too aggressive for the operating environment.The performance targets may be further provided as an input tosubsequent power management control phases, along with associatedconfiguration settings.

In some embodiments, during the second phase power management logic 1190is execute one or more power-performance algorithm to detect significantchanges in the workloads processed (e.g., associated with a displaytransition between partial and full screen rendering). In response todetecting such a change, power management logic 1190 is to re-evaluatethe performance characteristics and targets selected during the secondphase. Hence, in the phased architecture all workload analysisalgorithms may be implemented together during the second phase, forexample with a dynamic frequency and power scaling (DFPS) unit.

In some embodiments, during a subsequent third phase, power managementlogic 1190 is to execute one or more power-performance algorithm toattain the performance targets determined in the second stage with theconfiguration defined in the first and second stages. At operation 1730,power state hardware controls, such as operating frequency targets(e.g., f_(GP,Req)) 1725, frequency thresholds (e.g., f_(CP,Cap))1735,and/or multipliers (e.g., f_(CP)/f_(GP)) 1745 are to be set. During thisthird phase, power management logic 1190 may set the power statehardware controls based on relevant power, current, and/or thermallimits. In some SoC embodiments, these limits are chip-level thermaland/or power constraints. Constraint information processed in the thirdphase may be received, for example, from a power controller blockresponsible for chip management. Hence, the power-performance managementalgorithms included in the third phase may modify operating frequencytargets (e.g., f_(GP,Req)) 1725 and thresholds 1735 in an effort tobalance the energy budget across various SoC resources (e.g., CP and GP)to best maintain the performance targets. In some embodiments, a phasethree algorithm implemented at operation 1730 overclocks one or moregraphics resources (e.g., with IA turbo boost technology) as needed toachieve a performance target, and as limited by processor power,current, and/or thermal limits of the SoC.

In some embodiments, during a subsequent fourth phase, power managementlogic 1190 is to execute one or more power-performance algorithm atoperation 1740 to process one or more event driven tasks. Eventsprocessed at operation 1740 may be non-workload specific conditions,such as a high temperature condition or other stress indication event.Such events, may for example, be received from an SoC power block. Inthe exemplary embodiment, sleep states of one or more graphics resources(e.g., rC6 duration 1755) are set by one or more algorithms during thefourth phase. Duty cycle control implemented during the fourth phase maymodify controls set by the earlier phases, overriding them inrecognition of a received event, such as a display flip interrupt or SOCinterrupt. Hence, phase four includes a last set of power managementalgorithms in the exemplary power management control loop depicted inFIG. 17. In some embodiments, event processing at phase four isinterrupt-based, while the preceding phases are timer-based. As receivedevents 1792 enter buffer 1790, a decision is made whether the event iscritical requiring the management loop to process the event immediately,or if it can stored until next time event. With each iteration of thepower management control loop, phase-four algorithms executed atoperation 1740 may process one or more events stored in buffer 1790. Apriority event may be handled, or simply a next non-critical event maybe popped off buffer 1790.

At operation 1750 power management logic 1190 is to output a controlsignal indicative of the set of power management control parametervalues assembled into control vector 1705 during the current managementloop iteration. With all power management control parameter values setthrough sequential execution all power-performance managementalgorithms, the control vector 1705 may be converted to one compatibleset of requests. The requests may be output directly to graphics andcentral processor hardware, or output as an update to one or moregraphics processor contexts stored in memory. The compatible set ofrequests are then implemented by the hardware for the duration of asubsequent power management evaluation interval, or each time thecorresponding graphics processor context is switched in during thesubsequent power management evaluation interval. Upon outputting thecontrol requests at operation 1750, power management logic 1190 is tobegin a subsequent power management control loop iteration with thefirst phase algorithms, and repeat the subsequent phases substantiallyas described above to arrive at a subsequent control vector for output.

In some embodiments, iteration of operations 1710-1750 is performed on aslow loop, for example generating a set of control parameter requestvalues every 50-150 milliseconds. This slow management loop may beintegrated with graphics processor contexts that enable fastworkload-specific switching of at least some control parameter values.Slow-loop processing may be utilized to determine global performancetargets on the slow management loop time scale, and to updatecontext-specific parameters that may be switched-in and out many timesduring one iteration of the power-performance management loop.

Phased Graphics Processor Management with GP Contexts

FIG. 18 is a parallel flow chart depicting interactions of components ina system managing power-performance of graphics workload processingassociated with multiple applications, in accordance with someembodiments. At time to, an application 1111, executing in a user spaceof an OS instantiated by central processor 1140, interfaces with a(kernel mode) graphics processor driver 1109 to open one or moregraphics processor connections at operation 1805. In an embodiment, forexample where application 1111 is a 3D game, at least a render contextand a compute context is requested at operation 1805. In response,driver 1109 allocates memory 1150 for at least two new graphicsprocessor contexts at operation 1810. In one exemplary embodiment, botha render context and a compute context are created at operation 1810.

At operation 1815, application 1111 sends a compute workload to graphicsprocessor 1080 (e.g., via graphics processor driver 1109). At operation1820, scheduler logic 1160 sends the compute workload for a time sliceon graphics processor resources 1170 along with a command stringswitching-in a compute resource configuration (e.g., at least anoperating frequency and power-gating configuration) as defined in thecompute context information stored in memory 1150. At operation 1825,graphics processor resources 1170 process the compute workload while inthe compute context configuration. Independently, power management logic1190 begins a next power management process 1860 at evaluation starttime t₁. In some embodiments, the power management process 1860comprises a plurality of ordered phases of algorithms processingperformance data previously generated by and/or collected for graphicsprocessor resources 1170.

At operation 1830, graphics processor resources 1170 output computeworkload results to memory 1150. At operation 1840, graphics processorresources 1170 further output performance data associated with runningthe compute context workload. The performance data is output foranalysis by power management logic 1190 during a subsequent evaluationinterval. At operation 1816, application 1111 sends a plurality ofrender workloads to graphics processor 1080 (e.g., via graphicsprocessor driver 1109). At operation 1821, scheduler logic 1160 sends afirst render workload for a time slice on graphics processor resources1170 along with a command string switching-in a resource defined therender context information stored in memory 1150. At operation 1826,graphics processor resources 1170 process the first render workloadwhile in the render context. At operation 1831, graphics processorresources 1170 output render workload results to memory 1150. Atoperation 1841, graphics processor resources 1170 further outputperformance data associated with running the render context workload forsubsequent analysis.

At operation 1822, scheduler logic 1160 sends a second render workloadfor a time slice on graphics processor resources 1170 along with acommand string maintaining the render resource configuration. Atoperation 1827, graphics processor resources 1170 process the secondrender workload while in the render context. At operation 1832, graphicsprocessor resources 1170 output render workload results to memory 1150.At operation 1842, graphics processor resources 1170 further outputperformance data associated with running the second render context forsubsequent analysis.

At operation 1817, application 1111 sends a compute workload to graphicsprocessor 1080. At time t₂, the DFPS performance evaluation intervalends, and the performance data collected at operations 1840, 1841, and1842 is now ready for evaluation during a subsequent evaluation interval(not depicted). Power management process 1860 ends, for example aftersequentially executing all phases of a power management loop once. Insome embodiments, the power management process averages all storedperformance data to determine one or more control parameter. In otherembodiments performance data associated with a first graphics processorcontext is evaluated independently from data associated with a secondcontext to determine one or more control parameter updates for thecontexts. In some embodiments, a control vector assembled during powermanagement process 1860 is output at operation 1846 as control parametervalues written out to memory 1150. The control parameter values outputat operation 1846, for example, update both the render and computecontexts stored in memory 1150. At operation 1824, a compute workload isscheduled for processing by graphics processor resources 1170. Theworkload is processed at operation 1829 using parameters defined in thecompute context updated at operation 1846. Power management process 1860continues to adjust control parameters to maintain performance targetswhile in the runtime phase (e.g., until a new application beginsrendering, or a full-screen transition occurs, etc.).

To the extent various operations or functions are described herein, theycan be described or defined as hardware circuitry, software code,instructions, configuration, and/or data. The content can be embodied inhardware logic, or as directly executable software (“object” or“executable” form), source code, high level shader code designed forexecution on a graphics engine, or low level assembly language code inan instruction set for a specific processor or graphics core. Thesoftware content of the embodiments described herein can be provided viaan article of manufacture with the content stored thereon, or via amethod of operating a communication interface to send data via thecommunication interface.

A non-transitory machine readable storage medium can cause a machine toperform the functions or operations described, and includes anymechanism that stores information in a form accessible by a machine(e.g., computing device, electronic system, etc.), such asrecordable/non-recordable media (e.g., read only memory (ROM), randomaccess memory (RAM), magnetic disk storage media, optical storage media,flash memory devices, etc.). A communication interface includes anymechanism that interfaces to any of a hardwired, wireless, optical,etc., medium to communicate to another device, such as a memory businterface, a processor bus interface, an Internet connection, a diskcontroller, etc. The communication interface is configured by providingconfiguration parameters or sending signals to prepare the communicationinterface to provide a data signal describing the software content. Thecommunication interface can be accessed via one or more commands orsignals sent to the communication interface.

Various components described can be a means for performing theoperations or functions described. Each component described hereinincludes software, hardware, or a combination of these. The componentscan be implemented as software modules, hardware modules,special-purpose hardware (e.g., application specific hardware,application specific integrated circuits (ASICs), digital signalprocessors (DSPs), etc.), embedded controllers, hardwired circuitry,etc.

As exemplified above, embodiments described herein may be implementedusing hardware elements, software elements, or a combination of both.Examples of hardware elements or modules include: processors,microprocessors, circuitry, circuit elements (e.g., transistors,resistors, capacitors, inductors, and so forth), integrated circuits,application specific integrated circuits (ASIC), programmable logicdevices (PLD), digital signal processors (DSP), field programmable gatearray (FPGA), logic gates, registers, semiconductor device, chips,microchips, chip sets, and so forth. Examples of software elements ormodules include: applications, computer programs, application programs,system programs, machine programs, operating system software,middleware, firmware, routines, subroutines, functions, methods,procedures, software interfaces, application programming interfaces(API), instruction sets, computing code, computer code, code segments,computer code segments, data words, values, symbols, or any combinationthereof. Determining whether an embodiment is implemented using hardwareelements and/or software elements may vary in accordance with any numberof factors considered for the choice of design, such as, but not limitedto: desired computational rate, power levels, heat tolerances,processing cycle budget, input data rates, output data rates, memoryresources, data bus speeds and other design or performance constraints.

One or more aspects of at least one embodiment may be implemented byrepresentative instructions stored on a machine-readable storage medium.Such instructions may reside, completely or at least partially, within amain memory and/or within a processor during execution thereof by themachine, the main memory and the processor portions storing theinstructions then also constituting a machine-readable storage media.Programmable logic circuitry may have registers, state machines, etc.configured by the processor implementing the computer readable media.Such logic circuitry, as programmed, may then be understood to bephysically transformed into a system falling within the scope of theembodiments described herein. Instructions representing various logicwithin the processor, which when read by a machine may also cause themachine to fabricate logic adhering to the architectures describedherein and/or to perform the techniques described herein. Suchrepresentations, known as cell designs, or IP cores, may be stored on atangible, machine-readable medium and supplied to various customers ormanufacturing facilities to load into the fabrication machines thatactually make the logic or processor.

While certain features set forth herein have been described withreference to embodiments, this description is not intended to beconstrued in a limiting sense. Besides what is described herein, variousmodifications can be made to the disclosed embodiments andimplementations of the invention without departing from their scope.Therefore, the illustrations and examples herein should be construed inan illustrative, and not a restrictive sense. The scope of thedisclosure should be measured solely by reference to the claims thatfollow.

The following paragraphs briefly describe some exemplary embodiments:

In one or more first embodiments, a system comprises a central processor(CP), a graphics processor (GP) communicatively coupled to the CP andincluding one or more GP resource, and an electronic memorycommunicatively coupled to at least the GP and to store a first graphicsprocessor (GP) context specifying a first hardware configuration of theone or more GP resources, and a second GP context specifying a secondhardware configuration of the one or more GP resources. The one or moreGP resources are to be configured in a first hardware configurationbased on the first GP context in response to the GP receiving a firstworkload, and are to process the first workload while in the firsthardware configuration. The one or more GP resources are to bereconfigured based on the second GP context in response to receiving asecond workload, and to process the second workload with the one or moreGP resources in the second hardware configuration.]

In furtherance of the first embodiments, the memory is to store thefirst GP context in association with a first application executable onthe CP, and store the second GP context in association with a secondapplication executable on the CP. The GP is to configure the one or moreGP resources based on the first GP context in response to receiving thefirst workload from the first application, and configure the one or moreGP resources based on the second GP context in response to receiving thesecond workload from the second application.

In furtherance of the first embodiments, the first and second GPcontexts each specify at least a power-gating configuration or anoperating frequency of the one or more GP resources.

In furtherance of the first embodiments, the system further comprisesworkload scheduling logic to schedule a switching of the one or more GPresources between the first and second hardware configurations incoordination with the first and second workload processing.

In furtherance of the first embodiments, the system further comprisespower management logic to perform an evaluation of one or more GP powermanagement algorithms associated with a first GP power managementevaluation time interval during which at least the first workload andsecond workload are processed, and update at least one of the first GPcontext or second GP context, or reconfigure the one or more GPresource, based on the evaluation.

In furtherance of the embodiment immediately above, the power managementlogic is to determine a dominant GP context associated with the greatestportion of the first GP power management evaluation time interval,employ in the one or more GP power management algorithms, a performancetarget associated with the dominant GP context in response to thedominant GP context occupying a threshold portion of the firstevaluation time interval, and employ in the one or more GP powermanagement algorithms, a performance target associated with an averagingover the evaluation time interval in response to the dominant GP contextfailing to occupy the threshold portion of the first evaluation timeinterval.

In furtherance of the first embodiments above, the power managementlogic is to enable or disable GP context control of the one or more GPresources over a second GP power management evaluation time interval inresponse to a number of contexts processed within the first evaluationtime interval exceeding a predetermined threshold.

In furtherance of the first embodiments above, the power managementlogic is to sequentially execute a GP power management control loop oncein each GP power management evaluation time interval, the loopcomprising an identification of the one or more GP resources that may bepower-gated without impacting performance of workload processing, adetermination of one or more performance targets associated withworkload processing, an identification of one or more target powerstates that achieve the one or more performance targets, and an outputof one or more hardware configuration parameter request indicative ofthe GP resource power-gating, performance targets, or target powerstates.

In furtherance of the first embodiments, the CP, GP and memory arecomponents of a system-on-chip (SoC), and the GP includes amicrocontroller with logic circuitry to schedule the first and secondworkloads on the one or more GP resources, perform an evaluation of oneor more GP power management algorithms associated with a first GP powermanagement evaluation time interval during which at least the firstworkload and second workload are processed, and update at least one ofthe first GP context or second GP context, or reconfigure the one ormore GP resource, based on the evaluation.

In one or more second embodiments, a computer-readable media, includesinstructions stored thereon, which when executed by a processing system,cause the system to perform a method, comprising storing a firstgraphics processor (GP) context in association with a first applicationexecuting on a computer system, the first GP context specifying a firsthardware configuration of one or more GP resources of the system,storing a second GP context in association with a second applicationexecuting on the system, the second GP context specifying secondhardware configuration of the one or more GP resource, controlling theone or more GP resources into a first hardware configuration based onthe first GP context in response to receiving a first workloadassociated with the first application, processing the first workloadwith the GP resources in the first hardware configuration, reconfiguringthe one or more GP resources into a second hardware configuration basedon the second GP context in response to receiving a second workloadassociated with the second application, and processing the secondworkload with the one or more GP resources in the second hardwareconfiguration.

In furtherance of the second embodiments above, the processing of thefirst workload is during a first time slice, the processing of thesecond workload is during a second time slice, and the method furthercomprises performing an evaluation of one or more GP power managementalgorithms associated with a first GP power management evaluation timeinterval that includes at least both the first and second time slices,and updating at least one of the first GP context or second GP context,or reconfiguring the one or more GP resource, based on the evaluation.

In furtherance of the second embodiments above, the media furthercomprises instructions to cause the processing system to further performthe method comprising determining a dominant GP context associated withthe greatest portion of the first GP power management evaluation timeinterval, employing, in the one or more GP power management algorithms,a performance target associated with the dominant GP context in responseto the dominant GP context occupying a threshold portion of the firstevaluation time interval, and employing, in the one or more GP powermanagement algorithms, a performance target associated with an averagingover the evaluation time interval in response to the dominant GP contextfailing to occupy the threshold portion of the first evaluation timeinterval.

In furtherance of the second embodiments above, the media furthercomprises instructions to cause the processing system to further performthe method comprising enabling or disabling GP context control of theone or more GP resources over a second GP power management evaluationtime interval in response to a number of contexts processed within thefirst evaluation time interval exceeding a predetermined threshold.

In furtherance of the second embodiment immediately above, the one ormore GP resources are reconfigured once, based on the GP powermanagement algorithm evaluation, for the duration of a second GP powermanagement evaluation time interval in response to disabling GP contextcontrol.

In one or more third embodiments, a system, comprises a centralprocessor (CP), and a graphics processor (GP) communicatively coupled tothe CP and including one or more GP resource, wherein the CP or GPincludes logic to sequentially determine a set of graphics processor(GP) hardware configuration parameter requests based on differentmanagement algorithms, and output the set of configuration parameterrequests to one or more graphics processor (GP) resources.

In furtherance of the third embodiments above, to sequentially determinethe configuration parameter set, the GP is to determine one or morefirst parameter values indicative of one or more GP resources notcontributing to performance of a workload that may be powered down,determine one or more second parameter values indicative of one or moreperformance targets associated with processing the workload with the oneor more GP resources that are not to be powered-down, and identify oneor more third parameter values indicative of target power states for theone or more GP resources powered-up needed to achieve the one or moreperformance targets.

In furtherance of the third embodiment immediately above, wherein tosequentially determine the configuration parameter set, the GP isfurther to process one or more non-workload-specific event-driven tasks,and modify at least one of the parameter values previously determinedfor the parameter set based on the event-driven task processing.

In furtherance of the third embodiments, one sequential determination ofa configuration parameter set is determined for each GP power managementinterval, and each sequential determination of a configuration parameterset is triggered periodically, or in response to an event.

In one or more fourth embodiments, a computer-readable media includesinstructions stored thereon, which when executed by a processing system,cause the system to perform a method, comprising sequentiallydetermining a set of graphics processor (GP) hardware configurationparameter requests, and outputting the set of configuration parameterrequests to one or more graphics processor (GP) resources.

In furtherance of the fourth embodiments, sequentially determining theconfiguration parameter set further comprises determining one or moreparameter values indicative one or more GP resources not contributing toperformance of a workload that may be powered down, determining one ormore parameter values indicative of one or more performance targetsassociated with processing the workload with the one or more GPresources powered-up, and identifying one or more parameter valuesindicative of target power states for the one or more GP resourcespowered-up needed to achieve the one or more performance targets.

In furtherance of the fourth embodiments, the media further comprisesinstructions, which when executed by the processing system, furthercause the system to perform the method further comprising processing oneor more non-workload-specific event-driven tasks, and modifying at leastone of the parameter values previously determined for the parameter setbased on the event-driven task processing.

In furtherance of the fourth embodiments, determining the one or moreparameter values indicative of the base level configuration, the one ormore performance targets, or the target power states, further comprisesstoring, in association with a first GP context, GP performance datagenerated when first workloads are processed with the one or more GPresource configured based on the first GP context, storing, inassociation with a second GP context, GP performance data generated whensecond workloads are processed with the one or more GP resourceconfigured based on the second GP context, and averaging the stored GPperformance data between the first and second GP contexts, or processingGP performance data associated with the first GP context independentlyfrom GP performance data associated with the second GP context.Outputting the configuration parameter set to one or more graphicsprocessor (GP) resources further comprises outputting to the one or moreGP hardware resource global configuration parameter requests determinedbased on the averaged GP performance data, or updating the first andsecond GP contexts with GP context-specific parameter values determinedbased on the independently processed GP performance data.

In one or more fifth embodiment, a computer-implemented method comprisesstoring a first graphics processor (GP) context in association with afirst application executing on a computer system, the first GP contextspecifying a first hardware configuration of one or more GP resources ofthe system, storing a second GP context in association with a secondapplication executing on the system, the second GP context specifyingsecond hardware configuration of the one or more GP resource,configuring the one or more GP resources based on the first GP contextin response to receiving a first workload associated with the firstapplication, processing the first workload with the GP resources in thefirst hardware configuration, reconfiguring the one or more GP resourcesbased on the second GP context in response to receiving a secondworkload associated with the second application, and processing thesecond workload with the one or more GP resources in the second hardwareconfiguration.

In furtherance of the fifth embodiments, the first and second GPcontexts each specify at least a power-gating configuration or anoperating frequency of the one or more GP resources.

In furtherance of the fifth embodiment immediately above, the first andsecond GP contexts each specify both the power-gating configuration andoperating frequency of the one or more GP resources, and further specifya maximum operating frequency of one or more central processor (CP)resources executing the first or second application, or an operatingfrequency multiplier associated with the one or more CP resources andthe one or more GP resources.

In furtherance of the fifth embodiments, the processing of the firstworkload is during a first time slice. The processing of the secondworkload is during a second time slice. The method further comprisesperforming an evaluation of one or more GP power management algorithmsassociated with a first GP power management evaluation time intervalthat includes at least both the first and second time slices, andupdating at least one of the first GP context or second GP context, orreconfiguring the one or more GP resource, based on the evaluation.

In furtherance of the fifth embodiment immediately above, the methodfurther comprises determining a dominant GP context associated with thegreatest portion of the first GP power management evaluation timeinterval, employing, in the one or more GP power management algorithms,a performance target associated with the dominant GP context in responseto the dominant GP context occupying a threshold portion of the firstevaluation time interval, and employing, in the one or more GP powermanagement algorithms, a performance target associated with an averagingover the evaluation time interval in response to the dominant GP contextfailing to occupy the threshold portion of the first evaluation timeinterval.

In furtherance of the fifth embodiment above, further comprisesdetermining a dominant GP context associated with the greatest portionof the first GP power management evaluation time interval, and enablingor disabling GP context control of the one or more GP resources over asecond GP power management evaluation time interval based on the portionof the first evaluation time interval occupied by the dominant GPcontext.

In furtherance of the fifth embodiment immediately above, the one ormore GP resources are reconfigured for each workload processed duringthe second GP power management evaluation time interval based on theassociated GP contexts in response to the dominant GP context occupyinga threshold portion of the first evaluation time interval, or the one ormore GP resources are reconfigured once, based on the GP powermanagement algorithm evaluation, for the duration of a second GP powermanagement evaluation time interval in response to disabling GP contextcontrol in response to the dominant GP context failing to occupy thethreshold portion of the first evaluation time interval.

In furtherance of the fifth embodiment above, the processing of thefirst workload is during a first GP context evaluation intervalassociated with the first GP context, and the method further comprisescontrolling the one or more GP resources during the first GP contextevaluation interval with a power management algorithm that maximizesperformance of the one or more GP resources, updating the first GPcontext with one or more performance targets determined during the firstevaluation interval as state information associated with the firstcontext, and reconfiguring the one or more GP resource based on theupdated first GP context in response to receiving another workloadassociated with the first application.

In furtherance of the fifth embodiment above, the method furthercomprises sequentially executing a GP power management control loop oncein each GP power management evaluation time interval, the loopcomprising identifying any of the one or more GP resources that may bepowered-down without impacting performance of workload processing,determining one or more performance targets associated with workloadprocessing, identifying one or more target power states to achieve theone or more performance targets, and outputting one or more hardwareconfiguration parameter indicative of GP resources to be power-gated,one or more performance targets, or target power states.

In furtherance of the fifth embodiment immediately above, wherein theidentifying any of the one or more GP resources that may be powered-downfurther comprises evaluating the one or more GP resources in the firsthardware configuration and identifying at least one of a media block,codec, or execution unit not contributing to the processing of the firstworkload, determining the one or more performance targets furthercomprises determining a maximum frame/second (fps) associated withprocessing the first workload, identifying the one or more target powerstates further comprises modifying the operating frequency of one ormore execution units based on the one or more performance targets, andoutputting the one or more hardware configuration parameter furthercomprises updating the stored first GP context with one or more GPconfiguration parameters indicative of powering down the at least onemedia block, codec, or execution unit, the maximum fps, and theoperating frequency of the one or more execution units.

In one or more sixth embodiment, computer-implemented power managementcontrol method comprises sequentially determining a set of graphicsprocessor (GP) hardware configuration parameters, and outputting theconfiguration parameter set to one or more graphics processor (GP)resources. Sequentially determining the configuration parameter setfurther comprises determining one or more parameter values indicative ofa base level configuration of GP resources needed by a workload, thebase level indicative of one or more GP resources not contributing toperformance of a workload that may be powered down, determining one ormore parameter values indicative of one or more performance targetsassociated with processing the workload with the one or more GPresources powered-up in the base level configuration, and identifyingone or more parameter values indicative of target power states for theone or more GP resources powered-up in the base level configurationneeded to achieve the one or more performance targets.

In furtherance of the sixth embodiment immediately above, sequentiallydetermining the parameter set further comprises processing one or morenon-workload-specific event-driven tasks, and modifying at least one ofthe parameter values previously determined for the parameter set basedon the event-driven task processing.

In furtherance of the sixth embodiment, one sequential determination ofa configuration parameter set is determined for each GP power managementinterval, and each sequential determination of a configuration parameterset is triggered periodically, or in response to an event.

In furtherance of the sixth embodiment, processing the one or morenon-workload-specific event-driven task further comprises popping one ormore event from a FIFO event buffer with each sequential determinationof one configuration parameter set.

In furtherance of the sixth embodiment, determining the one or moreparameter values indicative of the base level configuration, the one ormore performance targets, or the target power states, further comprisesstoring, in association with a first GP context, GP performance datagenerated when first workloads are processed with the one or more GPresource configured based on the first GP context, storing, inassociation with a second GP context, GP performance data generated whensecond workloads are processed with the one or more GP resourceconfigured based on the second GP context, and averaging the stored GPperformance data between the first and second GP contexts, or processingGP performance data associated with the first GP context independentlyfrom GP performance data associated with the second GP context.Outputting the configuration parameter set to one or more graphicsprocessor (GP) resources further comprises outputting to the one or moreGP hardware resource global configuration parameter values determinedbased on the averaged GP performance data, or updating the first andsecond GP contexts with GP context-specific parameter values determinedbased on the independently processed GP performance data.

In one or more seventh embodiment, a computer-readable media includesinstructions stored thereon, which when executed by a processing system,cause the system to perform any one of the fifth embodiments.

In one or more eighth embodiment, a system comprises a computerizedmeans to perform any one of the fifth embodiments.

It will be recognized that the embodiments are not limited to theexemplary embodiments so described, but can be practiced withmodification and alteration without departing from the scope of theappended claims. For example, the above embodiments may include specificcombination of features. However, the above embodiments are not limitedin this regard and, in embodiments, the above embodiments may includeundertaking only a subset of such features, undertaking a differentorder of such features, undertaking a different combination of suchfeatures, and/or undertaking additional features than those featuresexplicitly listed. Scope should, therefore, be determined with referenceto the appended claims, along with the full scope of equivalents towhich such claims are entitled.

1. (canceled)
 2. A system, comprising: a central processor (CP); and agraphics processor (GP) communicatively coupled to the CP and includingone or more GP resource, wherein the CP or GP includes logic to:sequentially determine a set of graphics processor (GP) hardwareconfiguration parameter requests based on different managementalgorithms; and output the set of configuration parameter requests toone or more graphics processor (GP) resources.
 3. The system of claim 2,wherein to sequentially determine the configuration parameter set, theGP is to determine one or more first parameter values indicative of oneor more GP resources not contributing to performance of a workload thatmay be powered down.
 4. The system of claim 3, wherein to sequentiallydetermine the configuration parameter set, the GP is to determine one ormore second parameter values indicative of one or more performancetargets associated with processing the workload with the one or more GPresources that are not to be powered-down.
 5. The system of claim 3,wherein to sequentially determine the configuration parameter set, theGP is to identify one or more third parameter values indicative oftarget power states for the one or more GP resources powered-up neededto achieve the one or more performance targets.
 6. The system of claim4, wherein to sequentially determine the configuration parameter set,the GP is further to process one or more non-workload-specificevent-driven tasks.
 7. The system of claim 5, wherein to sequentiallydetermine the configuration parameter set, the GP is further to modifyat least one of the parameter values previously determined for theparameter set based on the event-driven task processing.
 8. The systemof claim 7, wherein one sequential determination of a configurationparameter set is determined for each GP power management interval. 9.The system of claim 8, wherein each sequential determination of aconfiguration parameter set is triggered periodically, or in response toan event.
 10. A computer-readable media, including instructions storedthereon, which when executed by a processing system, cause the system toperform a method, comprising: sequentially determining a set of graphicsprocessor (GP) hardware configuration parameter requests; and outputtingthe set of configuration parameter requests to one or more graphicsprocessor (GP) resources.
 11. The media of claim 10, whereinsequentially determining the configuration parameter set furthercomprises: determining one or more parameter values indicative one ormore GP resources not contributing to performance of a workload that maybe powered down.
 12. The media of claim 11, wherein sequentiallydetermining the configuration parameter set further comprises:determining one or more parameter values indicative of one or moreperformance targets associated with processing the workload with the oneor more GP resources powered-up.
 13. The media of claim 12, whereinsequentially determining the configuration parameter set furthercomprises: identifying one or more parameter values indicative of targetpower states for the one or more GP resources powered-up needed toachieve the one or more performance targets.
 14. The media of claim 13,further comprising instructions, which when executed by the processingsystem, further cause the system to perform the method furthercomprising: processing one or more non-workload-specific event-driventasks.
 15. The media of claim 14 further comprising instructions, whichwhen executed by the processing system, further cause the systemmodifying at least one of the parameter values previously determined forthe parameter set based on the event-driven task processing.
 16. Themedia of claim 19, wherein determining the one or more parameter valuesindicative of the base level configuration, the one or more performancetargets, or the target power states, further comprises: storing, inassociation with a first GP context, GP performance data generated whenfirst workloads are processed with the one or more GP resourceconfigured based on the first GP context.
 17. The media of claim 17,wherein determining the one or more parameter values indicative of thebase level configuration, the one or more performance targets, or thetarget power states, further comprises: storing, in association with asecond GP context, GP performance data generated when second workloadsare processed with the one or more GP resource configured based on thesecond GP context.
 18. The media of claim 18, wherein determining theone or more parameter values indicative of the base level configuration,the one or more performance targets, or the target power states, furthercomprises: averaging the stored GP performance data between the firstand second GP contexts, or processing GP performance data associatedwith the first GP context independently from GP performance dataassociated with the second GP context.
 19. The media of claim 19,wherein outputting the configuration parameter set to one or moregraphics processor (GP) resources further comprises: outputting to theone or more GP hardware resource global configuration parameter requestsdetermined based on the averaged GP performance data; or updating thefirst and second GP contexts with GP context-specific parameter valuesdetermined based on the independently processed GP performance data. 20.An apparatus, comprising: a first processor; and a second processorcommunicatively coupled to the first processor, wherein the secondprocessor includes one or more graphics processor resources, wherein thefirst or second processors include circuitry to: sequentially determinea set of hardware configuration parameter requests based on differentmanagement algorithms, wherein to sequentially determine the set ofhardware configuration parameter requests, the second processor is todetermine one or more parameter values indicative of the one or moregraphics processor resource that do not contribute to performance of aworkload that may be powered down; and output the set of configurationparameter requests to the one or more graphics processor resources. 21.The apparatus of claim 20, wherein the one or more parameter values arefirst one or more parameter values, and wherein to sequentiallydetermine the configuration parameter set, the second processor is todetermine one or more second parameter values indicative of one or moreperformance targets associated with processing the workload with the oneor more graphics processor resources that are not to be powered-down.